refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](OpenXiangShan/CoupledL2#251 (comment)).

src/main/scala/xiangshan/backend/Backend.scala

@@ -23,7 +23,6 @@ import device.MsiInfoBundle
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import system.HasSoCParameter
 import utility._
-import utils.{HPerfMonitor, HasPerfEvents, PerfEvent}
 import xiangshan._
 import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals}
 import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}

src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala

@@ -5,8 +5,7 @@ import chisel3.experimental.SourceInfo
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.rocket.CSRs
-import utility.SignExt
-import utils.PerfEvent
+import utility.{SignExt, PerfEvent}
 import xiangshan.backend.fu.NewCSR.CSRBundles._
 import xiangshan.backend.fu.NewCSR.CSRDefines._
 import xiangshan.backend.fu.NewCSR.CSRDefines.{CSRROField => RO, CSRRWField => RW, _}

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -6,8 +6,8 @@ import difftest._
 import freechips.rocketchip.rocket.CSRs
 import org.chipsalliance.cde.config.Parameters
 import top.{ArgParser, Generator}
-import utility.{DataHoldBypass, DelayN, GatedValidRegNext, RegNextWithEnable, SignExt, ZeroExt}
-import utils.{HPerfMonitor, OptionWrapper, PerfEvent}
+import utility.{DataHoldBypass, DelayN, GatedValidRegNext, RegNextWithEnable, SignExt, ZeroExt, HPerfMonitor, PerfEvent}
+import utils.OptionWrapper
 import xiangshan.backend.fu.NewCSR.CSRBundles.{CSRCustomState, PrivState, RobCommitCSR}
 import xiangshan.backend.fu.NewCSR.CSRDefines._
 import xiangshan.backend.fu.NewCSR.CSREnumTypeImplicitCast._
@@ -1048,13 +1048,6 @@ class NewCSR(implicit val p: Parameters) extends Module
     hcEvents(i) := io.perf.perfEventsHc(i)
   }
 
-  val allHcPerfEvents = hcEvents.map(x => (s"Hc", x.value))
-  if (printEventCoding) {
-    for (((name, inc), i) <- allHcPerfEvents.zipWithIndex) {
-      println("HuanCun perfEvents Set", name, inc, i)
-    }
-  }
-
   val hpmHc = HPerfMonitor(csrevents, hcEvents)
 
   val privState1H = Cat(privState.isModeM, privState.isModeHS, privState.isModeHU, privState.isModeVS, privState.isModeVU)

src/main/scala/xiangshan/backend/issue/Scheduler.scala

@@ -4,7 +4,8 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
-import utils.{HasPerfEvents, OptionWrapper}
+import utility.HasPerfEvents
+import utils.OptionWrapper
 import xiangshan._
 import xiangshan.backend.Bundles._
 import xiangshan.backend.datapath.DataConfig._

src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala

@@ -20,8 +20,7 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.ClientMetadata
-import utils.HasPerfEvents
-import utility.{ParallelPriorityMux, OneHot, ChiselDB, ParallelORR, ParallelMux, XSDebug, XSPerfAccumulate}
+import utility.{ParallelPriorityMux, OneHot, ChiselDB, ParallelORR, ParallelMux, XSDebug, XSPerfAccumulate, HasPerfEvents}
 import xiangshan.{XSCoreParamsKey, L1CacheErrorInfo}
 import xiangshan.cache.wpu._
 import xiangshan.mem.HasL1PrefetchSourceParameter

src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala

@@ -20,8 +20,8 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.{TLBundleB, TLEdgeOut, TLMessages, TLPermissions}
-import utils.{HasPerfEvents, HasTLDump}
-import utility.{XSDebug, XSPerfAccumulate}
+import utils.HasTLDump
+import utility.{XSDebug, XSPerfAccumulate, HasPerfEvents}
 
 class ProbeReq(implicit p: Parameters) extends DCacheBundle
 {

src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala

@@ -21,8 +21,8 @@ import chisel3.util._
 import freechips.rocketchip.tilelink.TLPermissions._
 import freechips.rocketchip.tilelink.{TLArbiter, TLBundleC, TLBundleD, TLEdgeOut}
 import org.chipsalliance.cde.config.Parameters
-import utils.{HasPerfEvents, HasTLDump}
-import utility.{XSDebug, XSPerfAccumulate}
+import utils.HasTLDump
+import utility.{XSDebug, XSPerfAccumulate, HasPerfEvents}
 
 
 class WritebackReqCtrl(implicit p: Parameters) extends DCacheBundle {

src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala

@@ -20,8 +20,7 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink.ClientMetadata
-import utils.HasPerfEvents
-import utility.{XSDebug, XSPerfAccumulate}
+import utility.{XSDebug, XSPerfAccumulate, HasPerfEvents}
 import xiangshan.L1CacheErrorInfo
 
 class DcacheStoreRequestIO(implicit p: Parameters) extends DCacheBundle {