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This repository has been archived by the owner on Sep 6, 2024. It is now read-only.

style: remove trailing whitespace #8

style: remove trailing whitespace

style: remove trailing whitespace #8

Workflow file for this run

name: fpga
on:
push:
workflow_dispatch:
jobs:
fpga:
runs-on: ubuntu-latest
steps:
- name: checkout repo
uses: actions/checkout@v4
with:
submodules: recursive
- name: FPGA bitstream for TT ASIC Sim (ICE40UP5K)
uses: TinyTapeout/tt-gds-action/fpga/ice40up5k@tt08