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Fix scripts used for running unit tests.
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vinaygangadhar committed Sep 16, 2015
1 parent aa62491 commit 6446365
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Showing 3 changed files with 62 additions and 29 deletions.
Empty file modified scripts/veriperl.pl
100644 → 100755
Empty file.
73 changes: 51 additions & 22 deletions src/sw/miaow_unit_tests/run
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,13 @@ use Getopt::Long;
#Declaration and initialization of variables
my $test = "";
my $script_name = $0;
my $m2s_ver = 0;
my $fpga;

$opt_result = GetOptions (
"input=s" => \$test,
"fpga" => \$fpga,
"version=s" => \$m2s_ver,
"help" => \$help,
);

Expand Down Expand Up @@ -45,15 +48,32 @@ if($fpga eq "") {

$t =~ s/\/$//;
$t =~ s/\/$//;
print $t;
print "$t\n";

my $cmd;
my $cp;

if($m2s_ver eq 2)
{
print "Using Multi2Sim 4.2 for compilation\n";
$cmd = "../../multi2sim-4.2/bin/m2s --si-debug-isa ${t}_trace --si-sim functional ut --load ut_Kernels.bin";
$cp = "cp ../lib/m2s-4.2/libm2s-opencl.so";
}
else
{
print "Using Multi2Sim 4.0 for compilation\n";
$cmd = "../../multi2sim-4.0/bin/m2s --si-debug-isa ${t}_trace --si-sim functional ut --load ut_Kernels.bin";
$cp = "cp ../lib/libm2s-opencl.so";
}

system "
cp ../lib/libm2s-opencl.so ./$t/;
cd ./common/;
$cp ./$t/;
cd ./common/;
cp ut ut_Kernels.bin ../$t/;
cd ../;
cd ./$t;
../../multi2sim-4.0/bin/m2s --si-debug-isa ${t}_trace --si-sim functional ut --load ut_Kernels.bin;
rm -f ut ut_Kernels.bin libm2s-opencl.so;
$cmd
rm -f ut ut_Kernels.bin libm2s-opencl.so;
../../common/trace_parser.pl -i ${t}_trace;
";
}
Expand All @@ -71,41 +91,43 @@ foreach $t (@list)
close INFILE;
chomp @c;

$fl = "stage_cu.c";
$fl = "unit_test_instr.fpga";

if (0 == open(OUTFILE, ">./$t/$fl"))
{
print STDERR "$script_name: Cannot open file $t/$fl for writing!\n";
die;
}

printf OUTFILE "void stage_cu()\n";
printf OUTFILE "{\n";

printf OUTFILE " // Writing instruction memory\n";

for($i = 1; $i < scalar(@c); $i+=4) {
printf OUTFILE " Xil_Out32(0x50001004, %d);\n", ($i-1);
printf OUTFILE " Xil_Out32(0x50001000, 0x%s%s%s%s);\n", $c[$i+3], $c[$i+2], $c[$i+1], $c[$i];;
printf OUTFILE "Xil_Out32(0x50001004, %d);\n", ($i-1);
printf OUTFILE "Xil_Out32(0x50001000, 0x%s%s%s%s);\n", $c[$i+3], $c[$i+2], $c[$i+1], $c[$i];;
}

close OUTFILE;

# generating sgpr files
open(INFILE, "./$t/unit_test_config.txt") or die "Could not open file";
@c = <INFILE>;
close INFILE;
chomp @c;

foreach($i = 1; $i < scalar(@c); $i++) {

printf OUTFILE "\n // Writing SGPRs for wavefront %d\n", $i;
$fl = "unit_test_sgpr_$i.fpga";
$l = $c[$i];

if (0 == open(OUTFILE, ">./$t/$fl"))
{
print STDERR "$script_name: Cannot open file $t/$fl for writing!\n";
die;
}

if($l =~ m/.*;S:(.*);.*/)
{
@slist = split(',', $1);
for($j = 0; $j < scalar(@slist); )
{
printf OUTFILE " Xil_Out32(0x50002004, %d);\n", ($j * 4);
printf OUTFILE "Xil_Out32(0x50002004, %d);\n", ($j * 4);

$s1 = $s2 = $s3 = $s4 = 0;

Expand All @@ -118,16 +140,18 @@ foreach $t (@list)
if($j < scalar(@slist)) { $s4 = (split('=', $slist[$j]))[1]; }
$j = $j + 1;

printf OUTFILE " Xil_Out32(0x50002008, 0x%X);\n", $s1;
printf OUTFILE " Xil_Out32(0x5000200C, 0x%X);\n", $s2;
printf OUTFILE " Xil_Out32(0x50002010, 0x%X);\n", $s3;
printf OUTFILE " Xil_Out32(0x50002014, 0x%X);\n", $s4;
printf OUTFILE "Xil_Out32(0x50002008, 0x%X);\n", $s1;
printf OUTFILE "Xil_Out32(0x5000200C, 0x%X);\n", $s2;
printf OUTFILE "Xil_Out32(0x50002010, 0x%X);\n", $s3;
printf OUTFILE "Xil_Out32(0x50002014, 0x%X);\n", $s4;

printf OUTFILE " Xil_Out32(0x50002000, 1);\n";
printf OUTFILE "Xil_Out32(0x50002000, 1);\n";
}
}

printf OUTFILE "}\n";



close OUTFILE
}
}
Expand All @@ -147,6 +171,11 @@ ARGUMENTS:
-i <input_test_name>
-input <input_test_name> This is a compulsory option; used to specify the name of test to be run.
-disasm Disassembly of Kernel Binary file
-v
-version Multi2sim version 0(default)[m2s4.0] 2[m2s4.2]
-h
-help Well, you know what this option is for! You couldn't be reading this otherwise.
};
Expand Down
18 changes: 11 additions & 7 deletions src/verilog/tb/run.pl
Original file line number Diff line number Diff line change
Expand Up @@ -87,15 +87,15 @@
if($killtime == 0)
{
#Setting default killtimes if not specified
if ($rdir eq "1")
if ($rdir =~ /^[1-5]$/)
{
#100 for unit tests
$killtime = 1000;
}
else
{
#A 100 million for benchmarks
$killtime = 100000000;
$killtime = 100000000000;
}
}
if(($outdir eq "") && (0 == $list))
Expand Down Expand Up @@ -128,13 +128,17 @@
{
$test_source = "../../sw/benchmarks";
}
elsif ("2" eq $rdir)
elsif ("6" eq $rdir)
{
$test_source = "../../sw/rodinia/opencl";
}
elsif ("1" eq $rdir)
elsif ("7" eq $rdir)
{
$test_source = "../../sw/miaow_unit_tests";
$test_source = "../../sw/AMDAPP_4.2";
}
elsif ($rdir =~ /^[1-5]$/)
{
$test_source = "../../sw/rand_unit_tests_".$rdir;
}
else
{
Expand Down Expand Up @@ -309,7 +313,7 @@ sub print_help
ARGUMENTS:
-r
-folder from which tests will be picked. Provide 0 for AMDAPP_benchmarks, 1 for miaow unit tests and 2 for Rodinia suite.
-folder from which tests will be picked. Provide 0 for AMDAPP_benchmarks, 1/2/3/4/5 for random tests, 6 for Rodinia suite and 7 for AMDAPP_4.2 version benchamrks.
-t
-test <testname/regex> This is a compulsory argument; used to specify the name of the unit test to be run. When this is a regular expression, it can select multiple tests
Expand Down Expand Up @@ -343,7 +347,7 @@ sub print_help
EXAMPLE USAGE:
$script_name -r 1 -t test_000_branch -o trial1
This will pick the test test_000_branch from miaow_unit_tests folder
This will pick the test test_000_branch from rand_unit_tests_1 folder
For above run, results can be found at /miaow/src/verilog/tb/results/trial1
$script_name -r 0 -t BinarySearch -o trial1
Expand Down

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