FPGA Functional Release
Pre-release
Pre-release
·
78 commits
to master
since this release
This update includes all of the infrastructure needed to synthesize MIAOW for use in a Xilinx VC707 evaluation board.
Corrected Issues:
- Identified the compilation bugs and resolved them
- Source Code fixes to memory module and testbench
- Added some FPGA related files and scripts
Apologies for the confusion with the initial release version.