Old TACO Working Version

Release Update:
This release update is the old version of MIAOW focused on testing benchmarks and Unit tests. This is intended for performing some case studies on MIAOW with working version of AMDAPP benchmarks. Please refer to Wiki for downloading the benchmarks.

Also, attached is the AMDAPP OpenCL benchmarks zipped folder. Please see "Running VCS simulations (unit tests and benchmarks):" section of BringUp and Verification wiki page on how to run these benchmarks.

Note: This release is not intended for FPGA mapping and users should use the FPGA release version for FPGA use.

Known Issues:

1. LSU-Memory bus width is impractical for FPGA mapping

FPGA Functional Release

This update includes all of the infrastructure needed to synthesize MIAOW for use in a Xilinx VC707 evaluation board.

Corrected Issues:

1. Identified the compilation bugs and resolved them
2. Source Code fixes to memory module and testbench
3. Added some FPGA related files and scripts

Apologies for the confusion with the initial release version.

Updated TACO code release

Fixed issues with unit tests scripts to allow for actual running of tests

HOTCHIPS conference code release

Updated code used for IEEE HOTCHIPS 2015 conference. LSU bus width between memory and register files has been significantly reduced to be synthesizable on FPGAs.

Known Issues:
Mismatch between wire/reg declaration and usage in sequential blocks. This primarily affects synthesis with Xilinx toolchains.
Current FPGA support framework does not work.
LSU lacks support for two and three dword operations.

Version associated with the ACM TACO Journal paper

Initial release of MIAOW code

Known Issues:

1. LSU-Memory bus width is impractical for FPGA mapping
2. Some of the unit tests are broken
3. veriperl.pl script does not have execute permissions