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Rename SIMD load splats and load extends #322

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Sep 8, 2020
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Rename SIMD load splats and load extends #322

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20 changes: 10 additions & 10 deletions interpreter/binary/decode.ml
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Expand Up @@ -222,16 +222,16 @@ let simd_prefix s =
let pos = pos s in
match vu32 s with
| 0x00l -> let a, o = memop s in v128_load a o
| 0x01l -> let a, o = memop s in i16x8_load8x8_s a o
| 0x02l -> let a, o = memop s in i16x8_load8x8_u a o
| 0x03l -> let a, o = memop s in i32x4_load16x4_s a o
| 0x04l -> let a, o = memop s in i32x4_load16x4_u a o
| 0x05l -> let a, o = memop s in i64x2_load32x2_s a o
| 0x06l -> let a, o = memop s in i64x2_load32x2_u a o
| 0x07l -> let a, o = memop s in v8x16_load_splat a o
| 0x08l -> let a, o = memop s in v16x8_load_splat a o
| 0x09l -> let a, o = memop s in v32x4_load_splat a o
| 0x0al -> let a, o = memop s in v64x2_load_splat a o
| 0x01l -> let a, o = memop s in v128_load8x8_s a o
| 0x02l -> let a, o = memop s in v128_load8x8_u a o
| 0x03l -> let a, o = memop s in v128_load16x4_s a o
| 0x04l -> let a, o = memop s in v128_load16x4_u a o
| 0x05l -> let a, o = memop s in v128_load32x2_s a o
| 0x06l -> let a, o = memop s in v128_load32x2_u a o
| 0x07l -> let a, o = memop s in v128_load8_splat a o
| 0x08l -> let a, o = memop s in v128_load16_splat a o
| 0x09l -> let a, o = memop s in v128_load32_splat a o
| 0x0al -> let a, o = memop s in v128_load64_splat a o
| 0x0bl -> let a, o = memop s in v128_store a o
| 0x0cl -> v128_const (at v128 s)
| 0x0dl -> v8x16_shuffle (List.init 16 (fun x -> u8 s))
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20 changes: 10 additions & 10 deletions interpreter/syntax/operators.ml
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Expand Up @@ -218,25 +218,25 @@ let memory_grow = MemoryGrow

(* SIMD *)
let v128_load align offset = SimdLoad {ty = V128Type; align; offset; sz = None}
let i16x8_load8x8_s align offset =
let v128_load8x8_s align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack8x8 SX)}
let i16x8_load8x8_u align offset =
let v128_load8x8_u align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack8x8 ZX)}
let i32x4_load16x4_s align offset =
let v128_load16x4_s align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack16x4 SX)}
let i32x4_load16x4_u align offset =
let v128_load16x4_u align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack16x4 ZX)}
let i64x2_load32x2_s align offset =
let v128_load32x2_s align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack32x2 SX)}
let i64x2_load32x2_u align offset =
let v128_load32x2_u align offset =
SimdLoad {ty = V128Type; align; offset; sz = Some (Pack64, Pack32x2 ZX)}
let v8x16_load_splat align offset =
let v128_load8_splat align offset =
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack8, PackSplat)}
let v16x8_load_splat align offset =
let v128_load16_splat align offset =
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack16, PackSplat)}
let v32x4_load_splat align offset =
let v128_load32_splat align offset =
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack32, PackSplat)}
let v64x2_load_splat align offset =
let v128_load64_splat align offset =
SimdLoad {ty= V128Type; align; offset; sz = Some (Pack64, PackSplat)}
let v128_store align offset = SimdStore {ty = V128Type; align; offset; sz = None}

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22 changes: 11 additions & 11 deletions interpreter/text/arrange.ml
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Expand Up @@ -409,8 +409,8 @@ let cvtop = oper (IntOp.cvtop, FloatOp.cvtop, SimdOp.cvtop)
let ternop = SimdOp.ternop

(* Temporary wart here while we finalize the names of SIMD loads and extends. *)
let memop ?(type_in_name=true) name {ty; align; offset; _} sz =
(if type_in_name then value_type ty ^ "." else "") ^ name ^
let memop name {ty; align; offset; _} sz =
value_type ty ^ "." ^ name ^
(if offset = 0l then "" else " offset=" ^ nat32 offset) ^
(if 1 lsl align = sz then "" else " align=" ^ nat (1 lsl align))

Expand All @@ -424,18 +424,18 @@ let simd_loadop (op : simd_loadop) =
match op.sz with
| None -> memop "load" op (size op.ty)
| Some (sz, pack_simd) ->
let prefix, suffix, ext =
let suffix =
(match sz, pack_simd with
| Pack64, Pack8x8 ext -> "i16x8", "8x8", extension ext
| Pack64, Pack16x4 ext -> "i32x4", "16x4", extension ext
| Pack64, Pack32x2 ext -> "i64x2", "32x2", extension ext
| Pack8, PackSplat -> "v8x16", "_splat", ""
| Pack16, PackSplat -> "v16x8", "_splat", ""
| Pack32, PackSplat -> "v32x4", "_splat", ""
| Pack64, PackSplat -> "v64x2", "_splat", ""
| Pack64, Pack8x8 ext -> "8x8" ^ extension ext
| Pack64, Pack16x4 ext -> "16x4" ^ extension ext
| Pack64, Pack32x2 ext -> "32x2" ^ extension ext
| Pack8, PackSplat -> "8_splat"
| Pack16, PackSplat -> "16_splat"
| Pack32, PackSplat -> "32_splat"
| Pack64, PackSplat -> "64_splat"
| _ -> assert false
) in
memop ~type_in_name:false (prefix ^ ".load" ^ suffix ^ ext) op (packed_size sz)
memop ("load" ^ suffix) op (packed_size sz)

let storeop op =
match op.sz with
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28 changes: 14 additions & 14 deletions interpreter/text/lexer.mll
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Expand Up @@ -288,20 +288,20 @@ rule token = parse
(ext s i64_load8_s i64_load8_u (opt a 0))
(ext s i64_load16_s i64_load16_u (opt a 1))
(ext s i64_load32_s i64_load32_u (opt a 2)) o)) }
| "i16x8.load8x8_"(sign as s)
{ LOAD (fun a o -> (ext s i16x8_load8x8_s i16x8_load8x8_u (opt a 3)) o) }
| "i32x4.load16x4_"(sign as s)
{ LOAD (fun a o -> (ext s i32x4_load16x4_s i32x4_load16x4_u (opt a 3)) o) }
| "i64x2.load32x2_"(sign as s)
{ LOAD (fun a o -> (ext s i64x2_load32x2_s i64x2_load32x2_u (opt a 3)) o) }
| "v8x16.load_splat"
{ LOAD (fun a o -> (v8x16_load_splat (opt a 0)) o) }
| "v16x8.load_splat"
{ LOAD (fun a o -> (v16x8_load_splat (opt a 1)) o) }
| "v32x4.load_splat"
{ LOAD (fun a o -> (v32x4_load_splat (opt a 2)) o) }
| "v64x2.load_splat"
{ LOAD (fun a o -> (v64x2_load_splat (opt a 3)) o) }
| "v128.load8x8_"(sign as s)
{ LOAD (fun a o -> (ext s v128_load8x8_s v128_load8x8_u (opt a 3)) o) }
| "v128.load16x4_"(sign as s)
{ LOAD (fun a o -> (ext s v128_load16x4_s v128_load16x4_u (opt a 3)) o) }
| "v128.load32x2_"(sign as s)
{ LOAD (fun a o -> (ext s v128_load32x2_s v128_load32x2_u (opt a 3)) o) }
| "v128.load8_splat"
{ LOAD (fun a o -> (v128_load8_splat (opt a 0)) o) }
| "v128.load16_splat"
{ LOAD (fun a o -> (v128_load16_splat (opt a 1)) o) }
| "v128.load32_splat"
{ LOAD (fun a o -> (v128_load32_splat (opt a 2)) o) }
| "v128.load64_splat"
{ LOAD (fun a o -> (v128_load64_splat (opt a 3)) o) }
| (ixx as t)".store"(mem_size as sz)
{ if t = "i32" && sz = "32" then error lexbuf "unknown operator";
STORE (fun a o ->
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20 changes: 10 additions & 10 deletions proposals/simd/BinarySIMD.md
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Expand Up @@ -33,16 +33,16 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
| Instruction | `simdop` | Immediate operands |
| ---------------------------|---------:|--------------------|
| `v128.load` | `0x00`| m:memarg |
| `i16x8.load8x8_s` | `0x01`| m:memarg |
| `i16x8.load8x8_u` | `0x02`| m:memarg |
| `i32x4.load16x4_s` | `0x03`| m:memarg |
| `i32x4.load16x4_u` | `0x04`| m:memarg |
| `i64x2.load32x2_s` | `0x05`| m:memarg |
| `i64x2.load32x2_u` | `0x06`| m:memarg |
| `v8x16.load_splat` | `0x07`| m:memarg |
| `v16x8.load_splat` | `0x08`| m:memarg |
| `v32x4.load_splat` | `0x09`| m:memarg |
| `v64x2.load_splat` | `0x0a`| m:memarg |
| `v128.load8x8_s` | `0x01`| m:memarg |
| `v128.load8x8_u` | `0x02`| m:memarg |
| `v128.load16x4_s` | `0x03`| m:memarg |
| `v128.load16x4_u` | `0x04`| m:memarg |
| `v128.load32x2_s` | `0x05`| m:memarg |
| `v128.load32x2_u` | `0x06`| m:memarg |
| `v128.load8_splat` | `0x07`| m:memarg |
| `v128.load16_splat` | `0x08`| m:memarg |
| `v128.load32_splat` | `0x09`| m:memarg |
| `v128.load64_splat` | `0x0a`| m:memarg |
| `v128.store` | `0x0b`| m:memarg |
| `v128.const` | `0x0c`| i:ImmByte[16] |
| `v8x16.shuffle` | `0x0d`| s:ImmLaneIdx32[16] |
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20 changes: 10 additions & 10 deletions proposals/simd/ImplementationStatus.md
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Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
| Instruction | LLVM[1] | V8[2] | WAVM[3] | ChakraCore[4] | SpiderMonkey[5] |
| ---------------------------|---------------------------|--------------------|--------------------|--------------------|--------------------|
| `v128.load` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i16x8.load8x8_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i16x8.load8x8_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i32x4.load16x4_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i32x4.load16x4_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i64x2.load32x2_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `i64x2.load32x2_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v8x16.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v16x8.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v32x4.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v64x2.load_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load8x8_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load8x8_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load16x4_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load16x4_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load32x2_s` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load32x2_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load8_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load16_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load32_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.load64_splat` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.store` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
| `v128.const` | `-munimplemented-simd128` | :heavy_check_mark: [6] | | | :heavy_check_mark: |
| `v8x16.shuffle` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
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20 changes: 10 additions & 10 deletions proposals/simd/NewOpcodes.md
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@@ -1,16 +1,16 @@
| Memory instruction | opcode |
| ------------------ | ------ |
| v128.load | 0x00 |
| i16x8.load8x8_s | 0x01 |
| i16x8.load8x8_u | 0x02 |
| i32x4.load16x4_s | 0x03 |
| i32x4.load16x4_u | 0x04 |
| i64x2.load32x2_s | 0x05 |
| i64x2.load32x2_u | 0x06 |
| v8x16.load_splat | 0x07 |
| v16x8.load_splat | 0x08 |
| v32x4.load_splat | 0x09 |
| v64x2.load_splat | 0x0a |
| v128.load8x8_s | 0x01 |
| v128.load8x8_u | 0x02 |
| v128.load16x4_s | 0x03 |
| v128.load16x4_u | 0x04 |
| v128.load32x2_s | 0x05 |
| v128.load32x2_u | 0x06 |
| v128.load8_splat | 0x07 |
| v128.load16_splat | 0x08 |
| v128.load32_splat | 0x09 |
| v128.load64_splat | 0x0a |
| v128.store | 0x0b |

| Basic operation | opcode |
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20 changes: 10 additions & 10 deletions proposals/simd/SIMD.md
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Expand Up @@ -768,10 +768,10 @@ def S.load(memarg):

### Load and Splat

* `v8x16.load_splat(memarg) -> v128`
* `v16x8.load_splat(memarg) -> v128`
* `v32x4.load_splat(memarg) -> v128`
* `v64x2.load_splat(memarg) -> v128`
* `v128.load8_splat(memarg) -> v128`
* `v128.load16_splat(memarg) -> v128`
* `v128.load32_splat(memarg) -> v128`
* `v128.load64_splat(memarg) -> v128`

Load a single element and splat to all lanes of a `v128` vector. The natural
alignment is the size of the element loaded.
Expand All @@ -784,12 +784,12 @@ def S.load_splat(memarg):

### Load and Extend

* `i16x8.load8x8_s(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane
* `i16x8.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane
* `i32x4.load16x4_s(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane
* `i32x4.load16x4_u(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane
* `i64x2.load32x2_s(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane
* `i64x2.load32x2_u(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane
* `v128.load8x8_s(memarg) -> v128`: load eight 8-bit integers and sign extend each one to a 16-bit lane
* `v128.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane
* `v128.load16x4_s(memarg) -> v128`: load four 16-bit integers and sign extend each one to a 32-bit lane
* `v128.load16x4_u(memarg) -> v128`: load four 16-bit integers and zero extend each one to a 32-bit lane
* `v128.load32x2_s(memarg) -> v128`: load two 32-bit integers and sign extend each one to a 64-bit lane
* `v128.load32x2_u(memarg) -> v128`: load two 32-bit integers and zero extend each one to a 64-bit lane

Fetch consecutive integers up to 32-bit wide and produce a vector with lanes up
to 64 bits. The natural alignment is 8 bytes.
Expand Down
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