Skip to content

Commit

Permalink
Merge pull request #4625 from povik/cellmatch-lut
Browse files Browse the repository at this point in the history
cellmatch: Size the `lut` attribute
  • Loading branch information
povik authored Oct 11, 2024
2 parents 0200a76 + ec42b42 commit a00137c
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion passes/techmap/cellmatch.cc
Original file line number Diff line number Diff line change
Expand Up @@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
for (auto bit : outputs) {
log_assert(bit.is_wire());
bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
bit.wire->attributes[ID(lut)] = luts[no++];
bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
}
}

Expand Down

0 comments on commit a00137c

Please sign in to comment.