Replace rlc with gap port bug fix

_unittest/test_00_EDB.py

@@ -1118,8 +1118,10 @@ def test_086_set_component_type(self):
         assert comp.type == "Other"
 
     def test_087_deactivate_rlc(self):
-        assert self.edbapp.components.deactivate_rlc_component(component="C1", create_circuit_port=True)
+        assert self.edbapp.components.deactivate_rlc_component(component="C1", create_circuit_port=False)
+        assert self.edbapp.ports["C1"]
         assert self.edbapp.components["C1"].is_enabled is False
+        assert self.edbapp.components.deactivate_rlc_component(component="C2", create_circuit_port=True)
         self.edbapp.components["C2"].is_enabled = False
         assert self.edbapp.components["C2"].is_enabled is False
         self.edbapp.components["C2"].is_enabled = True

pyaedt/edb_core/components.py

@@ -1057,7 +1057,7 @@
         >>> from pyaedt import Edb
         >>> edb_file = r'C:\my_edb_file.aedb'
         >>> edb = Edb(edb_file)
-        >>> for cmp in list(edb.components.components.keys()):
+        >>> for cmp in list(edb.components.instances.keys()):
         >>>     edb.components.deactivate_rlc_component(component=cmp, create_circuit_port=False)
         >>> edb.save_edb()
         >>> edb.close_edb()
@@ -1078,12 +1078,10 @@
             self._logger.info("Component %s passed to deactivate is not an RLC.", component.refdes)
             return False
         component.is_enabled = False
-        if create_circuit_port:
-            return self.add_port_on_rlc_component(component.refdes)
-        return True
+        return self.add_port_on_rlc_component(component=component.refdes, circuit_ports=create_circuit_port)
 
     @pyaedt_function_handler()
-    def add_port_on_rlc_component(self, component=None):
+    def add_port_on_rlc_component(self, component=None, circuit_ports=True):
         """Deactivate RLC component and replace it with a circuit port.
         The circuit port supports only 2-pin components.
 
@@ -1092,6 +1090,10 @@
         component : str
             Reference designator of the RLC component.
 
+        circuit_ports : bool
+            ``True`` will replace RLC component by circuit ports, ``False`` gap ports compatible with HFSS 3D modeler
+            export.
+
         Returns
         -------
         bool
@@ -1108,35 +1110,43 @@
             pt = self._pedb.point_data(*pos_pin_loc)
 
             pin_layers = self._padstack._get_pin_layer_range(pins[0])
-            pos_pin_term = self._pedb.edb_api.cell.terminal.PointTerminal.Create(
+            pos_pin_term = self._pedb.edb_api.cell.terminal.PadstackInstanceTerminal.Create(
                 self._active_layout,
                 pins[0].GetNet(),
                 "{}_{}".format(component.refdes, pins[0].GetName()),
-                pt,
+                pins[0],
                 pin_layers[0],
+                False,
             )
             if not pos_pin_term:  # pragma: no cover
                 return False
             neg_pin_loc = self.get_pin_position(pins[1])
             pt = self._pedb.point_data(*neg_pin_loc)
 
-            neg_pin_term = self._pedb.edb_api.cell.terminal.PointTerminal.Create(
+            neg_pin_term = self._pedb.edb_api.cell.terminal.PadstackInstanceTerminal.Create(
                 self._active_layout,
                 pins[1].GetNet(),
                 "{}_{}_ref".format(component.refdes, pins[1].GetName()),
-                pt,
+                pins[1],
                 pin_layers[0],
+                False,
             )
             if not neg_pin_term:  # pragma: no cover
                 return False
             pos_pin_term.SetBoundaryType(self._pedb.edb_api.cell.terminal.BoundaryType.PortBoundary)
-            pos_pin_term.SetIsCircuitPort(True)
             pos_pin_term.SetName(component.refdes)
             neg_pin_term.SetBoundaryType(self._pedb.edb_api.cell.terminal.BoundaryType.PortBoundary)
-            neg_pin_term.SetIsCircuitPort(True)
             pos_pin_term.SetReferenceTerminal(neg_pin_term)
+            if circuit_ports:
+                pos_pin_term.SetIsCircuitPort(True)
+                neg_pin_term.SetIsCircuitPort(True)
+            else:
+                pos_pin_term.SetIsCircuitPort(False)
+                neg_pin_term.SetIsCircuitPort(False)
+
             self._logger.info("Component {} has been replaced by port".format(component.refdes))
             return True
+        return False
 
     @pyaedt_function_handler()
     def add_rlc_boundary(self, component=None, circuit_type=True):