Add pre-process step and a driver function to the test infrastructure #664
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hydrolarus
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Since this rewrites all the tests using VexRiscv to be programmed before HITL test start it needs to access all FPGAs via JTAG, but #649 blocks this, so the software clock control HITL test is blocked on that. |
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This adds a pre-process and driver function to HITL tests as well as re-order some code.