✨ Support defects in the SiDB Gate Designer (#289)

* ✨ support defects in the SiDB Gate Designer

* 🎨 update docu.

* 🎨 delete redundant line.

* 🎨 implement Marcel's suggestions.

include/fiction/algorithms/physical_design/design_sidb_gates.hpp

@@ -123,7 +123,6 @@ class design_sidb_gates_impl
             if (!are_sidbs_too_close(combination))
             {
                 auto layout_with_added_cells = skeleton_layout_with_canvas_sidbs(combination);
-
                 if (const auto [status, sim_calls] =
                         is_operational(layout_with_added_cells, truth_table, params_is_operational);
                     status == operational_status::OPERATIONAL)
@@ -317,8 +316,8 @@ class design_sidb_gates_impl
 
 /**
  * The *SiDB Gate Designer* designs SiDB gate implementations based on a specified Boolean function, a
- * skeleton structure, canvas size, and a predetermined number of canvas SiDBs. Two different design modes are
- * implemented: `exhaustive` and `random design`.
+ * skeleton layout (can hold defects), canvas size, and a predetermined number of canvas SiDBs. Two different design
+ * modes are implemented: `exhaustive` and `random design`.
  *
  * The `exhaustive design` is composed of three steps:
  * 1. In the initial step, all possible distributions of `number_of_sidbs` SiDBs within a given canvas are

include/fiction/algorithms/simulation/sidb/random_sidb_layout_generator.hpp

@@ -129,10 +129,19 @@ Lyt generate_random_sidb_layout(const Lyt& lyt_skeleton, const generate_random_s
                     }
                 });
         }
-        // if the constraint that no positive SiDBs occur is satisfied, the SiDB is added to the layout
-        if (!constraint_violation_positive_sidbs)
+
+        bool random_cell_is_identical_wih_defect = false;
+        // check if a defect does not yet occupy random coordinate.
+        if constexpr (has_get_sidb_defect_v<Lyt>)
+        {
+            random_cell_is_identical_wih_defect = (lyt.get_sidb_defect(random_coord).type != sidb_defect_type::NONE);
+        }
+
+        // if the constraints that no positive SiDBs occur and the cell is not yet occupied by a defect are satisfied,
+        // the SiDB is added to the layout
+        if (!constraint_violation_positive_sidbs && !random_cell_is_identical_wih_defect)
         {
-            lyt.assign_cell_type(random_coord, Lyt::cell_type::NORMAL);
+            lyt.assign_cell_type(random_coord, technology<Lyt>::cell_type::NORMAL);
         }
         attempt_counter += 1;
     }

include/fiction/technology/sidb_surface.hpp

@@ -105,6 +105,18 @@ class sidb_surface<Lyt, false> : public Lyt
 
         assert(strg->params.ignore.count(sidb_defect_type::NONE) == 0 && "The defect type 'NONE' cannot be ignored");
     }
+    /**
+     * Clones the layout returning a deep copy.
+     *
+     * @return Deep copy of the layout.
+     */
+    [[nodiscard]] sidb_surface clone() const noexcept
+    {
+        sidb_surface copy{Lyt::clone()};
+        copy.strg = std::make_shared<sidb_surface_storage>(*strg);
+
+        return copy;
+    }
     /**
      * Assigns a given defect type to the given coordinate.
      *

test/algorithms/physical_design/design_sidb_gates.cpp

@@ -44,7 +44,7 @@ TEST_CASE("Use SiQAD XNOR skeleton and generate SiQAD XNOR gate, exhaustive", "[
 
     const design_sidb_gates_params params{sidb_simulation_parameters{2, -0.32},
                                           design_sidb_gates_params::design_sidb_gates_mode::EXHAUSTIVE,
-                                          {{10, 4, 0}, {10, 5, 1}},
+                                          {{10, 4, 0}, {10, 4, 0}},
                                           1,
                                           sidb_simulation_engine::QUICKEXACT};
 
@@ -134,20 +134,46 @@ TEST_CASE("Use FO2 Bestagon gate without SiDB at {17, 11, 0} and generate origin
     lyt.assign_cell_type({36, 19, 0}, sidb_technology::cell_type::NORMAL);
     lyt.assign_cell_type({2, 19, 0}, sidb_technology::cell_type::NORMAL);
 
-    CHECK(lyt.get_cell_type({17, 11, 0}) == layout::technology::EMPTY);
-
-    // generate gate by placing one SiDB
     const design_sidb_gates_params params{sidb_simulation_parameters{2, -0.32},
                                           design_sidb_gates_params::design_sidb_gates_mode::EXHAUSTIVE,
                                           {{17, 11, 0}, {17, 11, 0}},
                                           1,
                                           sidb_simulation_engine::QUICKEXACT};
 
-    const auto found_gate_layouts = design_sidb_gates(lyt, std::vector<tt>{create_fan_out_tt()}, params);
+    SECTION("generate original FO2")
+    {
+        CHECK(lyt.get_cell_type({17, 11, 0}) == layout::technology::EMPTY);
 
-    REQUIRE(found_gate_layouts.size() == 1);
-    CHECK(found_gate_layouts[0].num_cells() == 21);
-    CHECK(found_gate_layouts[0].get_cell_type({17, 11, 0}) == layout::technology::NORMAL);
+        // generate gate by placing one SiDB
+
+        const auto found_gate_layouts = design_sidb_gates(lyt, std::vector<tt>{create_fan_out_tt()}, params);
+
+        REQUIRE(found_gate_layouts.size() == 1);
+        CHECK(found_gate_layouts[0].num_cells() == 21);
+        CHECK(found_gate_layouts[0].get_cell_type({17, 11, 0}) == layout::technology::NORMAL);
+    }
+
+    SECTION("replace the output perturbers by equivalent negatively charged defects")
+    {
+        sidb_defect_cell_clk_lyt_siqad defect_layout{lyt};
+        defect_layout.assign_cell_type({36, 19, 0}, technology<sidb_defect_cell_clk_lyt_siqad>::cell_type::EMPTY);
+        defect_layout.assign_cell_type({2, 19, 0}, technology<sidb_defect_cell_clk_lyt_siqad>::cell_type::EMPTY);
+        CHECK(defect_layout.get_cell_type({36, 19, 0}) == technology<sidb_defect_cell_clk_lyt_siqad>::cell_type::EMPTY);
+        CHECK(defect_layout.get_cell_type({2, 19, 0}) == technology<sidb_defect_cell_clk_lyt_siqad>::cell_type::EMPTY);
+
+        defect_layout.assign_sidb_defect(
+            {36, 19, 0},
+            sidb_defect{sidb_defect_type::DB, -1, params.phys_params.epsilon_r, params.phys_params.lambda_tf});
+        defect_layout.assign_sidb_defect({2, 19, 0}, sidb_defect{sidb_defect_type::DB, -1, params.phys_params.epsilon_r,
+                                                                 params.phys_params.lambda_tf});
+
+        const auto found_gate_layouts = design_sidb_gates(defect_layout, std::vector<tt>{create_fan_out_tt()}, params);
+
+        REQUIRE(found_gate_layouts.size() == 1);
+        CHECK(found_gate_layouts[0].num_cells() == 19);
+        CHECK(found_gate_layouts[0].get_cell_type({17, 11, 0}) ==
+              technology<sidb_defect_cell_clk_lyt_siqad>::cell_type::NORMAL);
+    }
 }
 
 TEST_CASE("Design AND Bestagon shaped gate", "[design-sidb-gates]")
@@ -194,4 +220,28 @@ TEST_CASE("Design AND Bestagon shaped gate", "[design-sidb-gates]")
         REQUIRE(!found_gate_layouts.empty());
         CHECK(found_gate_layouts.front().num_cells() == lyt.num_cells() + 3);
     }
+
+    SECTION("Random Generation with defects")
+    {
+        sidb_defect_cell_clk_lyt_siqad defect_layout{lyt};
+
+        defect_layout.assign_sidb_defect(
+            {15, 10, 0},
+            sidb_defect{sidb_defect_type::DB, -1, params.phys_params.epsilon_r, params.phys_params.lambda_tf});
+        defect_layout.assign_sidb_defect(
+            {20, 12, 0},
+            sidb_defect{sidb_defect_type::DB, -1, params.phys_params.epsilon_r, params.phys_params.lambda_tf});
+
+        const auto found_gate_layouts = design_sidb_gates(defect_layout, std::vector<tt>{create_and_tt()}, params);
+        REQUIRE(!found_gate_layouts.empty());
+        CHECK(found_gate_layouts.front().num_defects() == 2);
+        CHECK(found_gate_layouts.front().num_cells() == lyt.num_cells() + 3);
+
+        found_gate_layouts.front().foreach_cell(
+            [](const auto& cell)
+            {
+                CHECK(cell != siqad::coord_t{15, 10, 0});
+                CHECK(cell != siqad::coord_t{20, 12, 0});
+            });
+    }
 }