User/dev/ekarabulut/fpga cw305

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-cedefe79d74c45c4d6bc37175e02f567b07bcc1e2a295c29caf6e92040bdb8e76ad1bf79db7c5652069e5697ebf90544
+6f6594cb7996fd411966e92096d3cd60987bd09303a5d144ac54854ea63c4d2bf37b10bc6f6dcd9ea996ab6e1f7b7ad2

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1729552312
+1729635845

src/mldsa_top/config/compile.yml

@@ -40,6 +40,7 @@ targets:
       - $COMPILE_ROOT/rtl/mldsa_seq_prim.sv
       - $COMPILE_ROOT/rtl/mldsa_seq_sec.sv
       - $COMPILE_ROOT/rtl/mldsa_ctrl.sv
+      - $COMPILE_ROOT/rtl/ntt_arbiter.sv
       - $COMPILE_ROOT/rtl/mldsa_top.sv
       - $COMPILE_ROOT/rtl/mldsa_reg.sv
     tops: [mldsa_top]

src/mldsa_top/rtl/mldsa_config_defines.svh

@@ -18,6 +18,7 @@
    `include "abr_sva.svh"
    // `define RV_FPGA_OPTIMIZE
    // `define RV_FPGA_SCA
+   // `define RV_CW305_FPGA_SCA
 
 
   `define ABR_ICG           abr_clk_gate

src/mldsa_top/rtl/mldsa_ctrl.sv

@@ -941,8 +941,14 @@ module mldsa_ctrl
       MLDSA_KG_JUMP_SIGN : begin
         //Jump to signing process
         if (keygen_signing_process) begin
-          prog_cntr_nxt = MLDSA_SIGN_S;
-          signing_process_nxt  = 1;
+          if (sign_prog_cntr == MLDSA_SIGN_CHECK_C_VLD) begin
+            prog_cntr_nxt = MLDSA_SIGN_S;
+            signing_process_nxt  = 1;
+          end
+          else begin
+            prog_cntr_nxt = MLDSA_KG_JUMP_SIGN;
+            signing_process_nxt  = 0;
+          end
         end
         else begin
           prog_cntr_nxt = prog_cntr + 1;

src/mldsa_top/rtl/ntt_arbiter.sv

@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+`include "mldsa_config_defines.svh"
+
+module ntt_arbiter 
+    import mldsa_params_pkg::*;
+    import mldsa_ctrl_pkg::*;
+    import ntt_defines_pkg::*;
+  (
+    input logic clk,
+    input logic reset_n,
+
+    // Inputs from controller
+    input logic [1:0] ntt_enable,           // ntt_enable[0] for NTT_0, ntt_enable[1] for NTT_1
+    input mldsa_ntt_mode_e [1:0] ntt_mode,
+    input ntt_mem_addr_t [1:0] ntt_mem_base_addr,
+    input pwo_mem_addr_t [1:0] pwo_mem_base_addr,
+
+    // Inputs from sampler
+    input logic [1:0] sampler_ntt_dv, 
+
+    // Inputs from NTT
+    input logic ntt_busy,
+    input logic ntt_done,
+
+    input mem_if_t ntt_mem_wr_req_i,
+    input mem_if_t ntt_mem_rd_req_i,
+    input logic [MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_wr_data_i,
+
+    input mem_if_t pwm_a_rd_req_i,
+    input mem_if_t pwm_b_rd_req_i,
+
+
+    // Outputs to memory MUX
+    output mem_if_t [1:0] ntt_mem_wr_req_o,
+    output mem_if_t [1:0] ntt_mem_rd_req_o,
+    output logic [1:0][MLDSA_MEM_DATA_WIDTH-1:0] ntt_mem_wr_data_o,
+
+    output mem_if_t [1:0] pwm_a_rd_req_o,
+    output mem_if_t [1:0] pwm_b_rd_req_o,
+
+    // Outputs to controller
+    output logic [1:0] ntt_busy_o,
+    output logic [1:0] ntt_done_o,
+
+    // Outputs to NTT
+    output logic ntt_enable_o,
+    output mode_t ntt_mode_o,
+    output logic accumulate_o,
+    output logic sampler_valid_o,
+    output logic sampler_ntt_mode_o,
+    output ntt_mem_addr_t ntt_mem_base_addr_o,
+    output pwo_mem_addr_t pwo_mem_base_addr_o
+  );
+
+  // Internal registers
+  logic [1:0] using_ntt;
+
+  logic ntt_enable_r;
+  mldsa_ntt_mode_e ntt_mode_r;
+  logic accumulate_r;
+  logic sampler_valid_r;
+  ntt_mem_addr_t ntt_mem_base_addr_r;
+  pwo_mem_addr_t pwo_mem_base_addr_r;
+
+  // Latch inputs and select NTT based on ntt_enable signals
+  always_ff @(posedge clk or negedge reset_n) begin
+      if (!reset_n) begin
+          using_ntt <= 0;
+          ntt_enable_r <= 0;
+          ntt_mode_r <= MLDSA_NTT_NONE;
+          ntt_mem_base_addr_r <= '0;
+          pwo_mem_base_addr_r <= '0;
+      end else begin
+            ntt_enable_o <= ntt_enable[0] | ntt_enable[1];
+            if (ntt_enable[0]) begin
+                using_ntt <= 1;
+                ntt_mode_r <= ntt_mode[0];
+                ntt_mem_base_addr_r <= ntt_mem_base_addr[0];
+                pwo_mem_base_addr_r <= pwo_mem_base_addr[0];
+            end else if (ntt_enable[1]) begin
+                using_ntt <= 2;
+                ntt_mode_r <= ntt_mode[1];
+                ntt_mem_base_addr_r <= ntt_mem_base_addr[1];
+                pwo_mem_base_addr_r <= pwo_mem_base_addr[1];
+            end
+      end
+  end
+
+  // Output logic to NTT engine
+  always_comb begin
+      if (using_ntt[0]) begin
+          //ntt_enable_o = ntt_enable_r;
+          ntt_mem_base_addr_o = ntt_mem_base_addr_r;
+          pwo_mem_base_addr_o = pwo_mem_base_addr_r;
+      end else begin
+        //   ntt_enable_o = ntt_enable[1];
+          ntt_mem_base_addr_o = ntt_mem_base_addr[1];
+          pwo_mem_base_addr_o = pwo_mem_base_addr[1];
+      end
+  end
+
+  // Output logic to controller
+  always_comb begin
+      ntt_busy_o = 2'b00;
+      ntt_done_o = 2'b00;
+      if (using_ntt[0]) begin
+          ntt_busy_o[0] = ntt_busy | (using_ntt[0] & ntt_enable_o);
+          ntt_done_o[0] = ntt_done;
+      end else begin
+          ntt_busy_o[1] = ntt_busy | (using_ntt[1] & ntt_enable_o);
+          ntt_done_o[1] = ntt_done;
+      end
+  end
+
+  always_comb begin
+
+    ntt_mem_wr_req_o[0] = ntt_mem_wr_req_i;
+    ntt_mem_rd_req_o[0] = ntt_mem_rd_req_i;
+    ntt_mem_wr_data_o[0] = ntt_mem_wr_data_i;
+    pwm_a_rd_req_o[0] = pwm_a_rd_req_i;
+    pwm_b_rd_req_o[0] = pwm_b_rd_req_i;
+
+    ntt_mem_wr_req_o[1] = '{rd_wr_en: RW_IDLE, addr: '0};
+    ntt_mem_rd_req_o[1] = '{rd_wr_en: RW_IDLE, addr: '0};
+    ntt_mem_wr_data_o[1] = '0;
+    pwm_a_rd_req_o[1]    = '{rd_wr_en: RW_IDLE, addr: '0};
+    pwm_b_rd_req_o[1]    = '{rd_wr_en: RW_IDLE, addr: '0};
+
+  end
+
+
+    always_comb begin
+        ntt_mode_o = '0;
+        accumulate_o = '0;
+        sampler_valid_o = 0;
+        sampler_ntt_mode_o = 0;
+
+      unique case (ntt_mode_r) inside
+        MLDSA_NTT_NONE: begin
+        end
+        MLDSA_NTT: begin
+            ntt_mode_o = ct;
+        end
+        MLDSA_INTT: begin
+            ntt_mode_o = gs;
+        end
+        MLDSA_PWM_SMPL: begin
+            ntt_mode_o = pwm;
+            sampler_valid_o = using_ntt[0] ? sampler_ntt_dv[0]: '0;
+            sampler_ntt_mode_o = 1;
+        end
+        MLDSA_PWM_ACCUM_SMPL: begin
+            ntt_mode_o = pwm;
+            accumulate_o = 1;
+            sampler_valid_o = using_ntt[0]? sampler_ntt_dv[0]: '0;
+            sampler_ntt_mode_o = 1;
+        end
+        MLDSA_PWM: begin
+            ntt_mode_o = pwm;
+            sampler_valid_o = 1;
+        end
+        MLDSA_PWM_ACCUM: begin
+            ntt_mode_o = pwm;
+            accumulate_o = 1;
+            sampler_valid_o = 1;
+        end
+        MLDSA_PWA: begin
+            ntt_mode_o = pwa;
+            sampler_valid_o = 1;
+        end
+        MLDSA_PWS: begin
+            ntt_mode_o = pws;
+            sampler_valid_o = 1;
+        end
+        default: begin
+        end
+      endcase 
+    end
+
+  endmodule
+

src/pk_decode/rtl/pkdecode.sv

@@ -50,6 +50,7 @@ module pkdecode
         output logic pkdecode_done
     );
 
+`ifndef RV_CW305_FPGA_SCA
     localparam COEFF_WIDTH = 10;
     localparam SHIFT_LEFT = 13;
     localparam NUM_COEFFS_PER_CYCLE = 8;
@@ -228,4 +229,15 @@ module pkdecode
         end
     end
 
+`else
+    always_comb begin
+        mem_a_wr_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        mem_b_wr_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        mem_a_wr_data = '0;
+        mem_b_wr_data = '0;
+        API_rd_address = '0;
+        pkdecode_done = '0;
+    end
+`endif
+
 endmodule

src/sig_decode_z/rtl/sigdecode_z_top.sv

@@ -57,7 +57,7 @@ module sigdecode_z_top
         input wire sigdecode_z_enable,
         output logic sigdecode_z_done
     );
-
+`ifndef RV_CW305_FPGA_SCA
     localparam THE_LAST_ADDR = ((MLDSA_L * MLDSA_N)/4)-1;
     // State Machine States
     localparam  IDLE                = 3'b000,
@@ -236,6 +236,16 @@ module sigdecode_z_top
         end : dec_unit
     endgenerate
 
-
+`else
+    always_comb begin
+        mem_a_wr_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        mem_b_wr_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        mem_a_wr_data = '0;
+        mem_b_wr_data = '0;
+        sigmem_a_rd_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        sigmem_b_rd_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        sigdecode_z_done = '0;
+    end
+`endif
 
 endmodule

src/sigdecode_h/rtl/sigdecode_h.sv

@@ -47,7 +47,7 @@ module sigdecode_h
     );
 
     localparam SIG_H_NUM_DWORDS = ((MLDSA_OMEGA + MLDSA_K + 1)*8)/32;
-
+`ifndef RV_CW305_FPGA_SCA
     // logic [(MLDSA_OMEGA+MLDSA_K)-1:0][7:0] encoded_h;
     // logic [SIG_H_NUM_DWORDS-1:0][31:0] encoded_h_reg;
     logic [MLDSA_OMEGA-1:0] hint_array;
@@ -140,4 +140,13 @@ module sigdecode_h
         .hint_rd_en(hint_rd_en)
     );
 
+
+`else
+    always_comb begin
+        mem_wr_req = '{rd_wr_en: RW_IDLE, addr: '0};
+        mem_wr_data = '0;
+        sigdecode_h_done = '0;
+        sigdecode_h_error = '0;
+    end
+`endif
 endmodule