initial round of lint fixes

chipsalliance · Mar 26, 2024 · 020cdc6 · 020cdc6
1 parent 33d49ab
commit 020cdc6
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Showing 6 changed files with 26 additions and 11 deletions.
diff --git a/src/integration/config/compile.yml b/src/integration/config/compile.yml
@@ -46,8 +46,6 @@ targets:
   rtl_lint:
     waiver_files:
       - $MSFT_REPO_ROOT/src/integration/config/design_lint/sglint_waivers
-    black_box:
-      - el2_veer_wrapper
   cdc:
     tcl_files:
       - $COMPILE_ROOT/config/cdc/integration_top.constraints.tcl

diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
@@ -324,8 +324,8 @@ end
         .hclk                          ( clk_cg                      ),
         .hreset_n                      ( cptra_noncore_rst_b         ),
         .force_bus_idle                ( fw_update_rst_window        ),
-        .ahb_lite_responders           ( responder_inst              ),
-        .ahb_lite_initiator            ( initiator_inst              ),
+        .ahb_lite_responders           ( responder_inst.Responder_Interface_Ports),
+        .ahb_lite_initiator            ( initiator_inst.Initiator_Interface_Ports),
         .ahb_lite_resp_disable_i       ( ahb_lite_resp_disable       ),
         .ahb_lite_resp_access_blocked_o( ahb_lite_resp_access_blocked),
         .ahb_lite_start_addr_i         ( `CALIPTRA_SLAVE_BASE_ADDR   ),

diff --git a/src/keyvault/rtl/kv_fsm.sv b/src/keyvault/rtl/kv_fsm.sv
@@ -155,22 +155,37 @@ always_ff @(posedge clk or negedge rst_b) begin
     if (!rst_b) begin
         kv_fsm_ps <= KV_IDLE;
         offset <= '0;
-        num_dwords_data <= '0;
     end
     else if (zeroize) begin
         kv_fsm_ps <= KV_IDLE;
         offset <= '0;
-        num_dwords_data <= '0;
     end
     else begin
         kv_fsm_ps <= kv_fsm_ns;
         offset <= offset_rst ? '0 :
                   offset_en ? offset_nxt : offset;
-        //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data
-        num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data;
     end
 end
 
+generate
+    if (PAD==1) begin
+        always_ff @(posedge clk or negedge rst_b) begin
+            if (!rst_b) begin
+                num_dwords_data <= '0;
+            end
+            else if (zeroize) begin
+                num_dwords_data <= '0;
+            end
+            else begin
+                //store the offset_nxt on the last cycle of valid data, this is the number of dwords of valid data
+                num_dwords_data <= arc_KV_RW_KV_PAD ? offset_nxt : num_dwords_data;
+            end
+        end
+    end else begin
+        always_comb num_dwords_data = '0;
+    end
+endgenerate
+
 always_comb read_offset = (kv_fsm_ps == KV_RW) ? offset[OFFSET_W-1:0] : '0;
 always_comb write_offset = offset[OFFSET_W-1:0];
 

diff --git a/src/pcrvault/rtl/pv_gen_hash.sv b/src/pcrvault/rtl/pv_gen_hash.sv
@@ -199,6 +199,7 @@ assign block_offset = block_offset_i[BLOCK_OFFSET_W-1:0];
     if (~rst_b) begin
       gen_hash_fsm_ps <= GEN_HASH_IDLE;
       block_offset_i <= '0;
+      nonce_offset_i <= '0;
       read_entry <= '0;
       read_offset <= '0;
     end

diff --git a/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv b/src/riscv_core/veer_el2/rtl/ifu/el2_ifu_mem_ctl.sv
@@ -923,9 +923,6 @@ logic                                         perr_sel_invalidate;
 logic                                         perr_sb_write_status   ;
 
 
-
-   rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff    (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status),  .*);
-
    assign perr_err_inv_way[pt.ICACHE_NUM_WAYS-1:0]   =  {pt.ICACHE_NUM_WAYS{perr_sel_invalidate}} ;
    assign iccm_correct_ecc     = (perr_state == ECC_CORR);
    assign dma_sb_err_state     = (perr_state == DMA_SB_ERR);
@@ -1407,6 +1404,8 @@ if (pt.ICACHE_ENABLE == 1 ) begin: icache_enabled
          assign way_status_new_w_debug[pt.ICACHE_STATUS_BITS-1:0]  = (ic_debug_wr_en  & ic_debug_tag_array) ? (pt.ICACHE_STATUS_BITS == 1) ? ic_debug_wr_data[4] : ic_debug_wr_data[6:4] :
                                                 way_status_new[pt.ICACHE_STATUS_BITS-1:0] ;
 
+   rvdffe #(.WIDTH(pt.ICACHE_INDEX_HI-pt.ICACHE_TAG_INDEX_LO+1),.OVERRIDE(1)) perr_dat_ff    (.din(ifu_ic_rw_int_addr_ff[pt.ICACHE_INDEX_HI:pt.ICACHE_TAG_INDEX_LO]), .dout(perr_ic_index_ff[pt.ICACHE_INDEX_HI : pt.ICACHE_TAG_INDEX_LO]), .en(perr_sb_write_status),  .*);
+
    rvdffie #(.WIDTH(pt.ICACHE_TAG_LO-pt.ICACHE_TAG_INDEX_LO+1+pt.ICACHE_STATUS_BITS),.OVERRIDE(1))  status_misc_ff
      (.*,
       .clk(free_l2clk),

diff --git a/src/soc_ifc/rtl/mbox.sv b/src/soc_ifc/rtl/mbox.sv
@@ -478,8 +478,10 @@ rvecc_encode mbox_ecc_encode (
     .ecc_out(sram_wdata_ecc)
 );
 // synthesis translate_off
+`ifdef CLP_ASSERT_ON 
 initial assert(DATA_W == 32) else
     $error("%m::rvecc_encode supports 32-bit data width; must change SRAM ECC implementation to support DATA_W = %d", DATA_W);
+`endif
 // synthesis translate_on
 rvecc_decode ecc_decode (
     .en              (sram_rd_ecc_en       ),