Synchronously de-assert asynchronous reset #428
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We can only model a synchronous deassertion of an asynchronous reset. This manifests itself when we use a reset synchronizer: When we do a synchronous deassertion of the reset, the HDL simulation and Clash simulation would differ; where the HDL simulation corresponds to how the actual circuit would behave. i.e. the Clash simulation was wrong! The reason for this is that we modeled a register with an asynchronous reset as if its reset line was always asynchronously deasserted. Given that we can only create synchronous systems in Clash, it made no sense that the model of the register behaved like this. We now model a register with an asynchronous reset as if its reset line is always synchronously deasserted, and the HDL primitive for the `asyncResetGen` is updated accordingly (i.e. it deasserts synchronously), so that the Clash and HDL simulation agree.
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We can only model a synchronous deassertion of an asynchronous reset. This manifests itself when we use a reset synchronizer: When we do a synchronous deassertion of the reset, the HDL simulation and Clash simulation would differ; where the HDL simulation corresponds to how the actual circuit would behave. i.e. the Clash simulation was wrong! The reason for this is that we modeled a register with an asynchronous reset as if its reset line was always asynchronously deasserted. Given that we can only create synchronous systems in Clash, it made no sense that the model of the register behaved like this. We now model a register with an asynchronous reset as if its reset line is always synchronously deasserted, and the HDL primitive for the `asyncResetGen` is updated accordingly (i.e. it deasserts synchronously), so that the Clash and HDL simulation agree.
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Jun 6, 2019
PR #428 does this for `assert`, but didn't account for `assertBitVector`.
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PR #428 does this for `assert`, but didn't account for `assertBitVector`.
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Jun 6, 2019
PR #428 does this for `assert`, but didn't account for `assertBitVector`. Also updates verilog/systemverilog blackboxes.
martijnbastiaan
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PR #428 does this for `assert`, but didn't account for `assertBitVector`. Also updates verilog/systemverilog blackboxes.
martijnbastiaan
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PR #428 does this for `assert`, but didn't account for `assertBitVector`. Also updates verilog/systemverilog blackboxes.
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We can only model a synchronous deassertion of an asynchronous reset. This manifests itself when we use a reset synchronizer:
When we do a synchronous deassertion of the reset, the HDL simulation and Clash simulation would differ; where the HDL simulation corresponds to how the actual circuit would behave. i.e. the Clash simulation was wrong!
The reason for this is that we modeled a register with an asynchronous reset as if its reset line was always asynchronously deasserted. Given that we can only create synchronous systems in Clash, it made no sense that the model of the register behaved like this.
We now model a register with an asynchronous reset as if its reset line is always synchronously deasserted, and the HDL primitive for the
asyncResetGenis updated accordingly (i.e. it deasserts synchronously), so that the Clash and HDL simulation agree.