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Synchronously de-assert asynchronous reset #428

Merged
merged 1 commit into from
Nov 23, 2018
Merged

Synchronously de-assert asynchronous reset #428

merged 1 commit into from
Nov 23, 2018

Commits on Nov 23, 2018

  1. Synchronous deassert asynchronous reset 

    We can only model a synchronous deassertion of an asynchronous
reset. This manifests itself when we use a reset synchronizer:

When we do a synchronous deassertion of the reset, the HDL simulation
and Clash simulation would differ; where the HDL simulation
corresponds to how the actual circuit would behave. i.e. the
Clash simulation was wrong!

The reason for this is that we modeled a register with an
asynchronous reset as if its reset line was always asynchronously
deasserted. Given that we can only create synchronous systems in
Clash, it made no sense that the model of the register behaved
like this.

We now model a register with an asynchronous reset as if its
reset line is always synchronously deasserted, and the HDL
primitive for the `asyncResetGen` is updated accordingly
(i.e. it deasserts synchronously), so that the Clash and HDL
simulation agree.
    @christiaanb
    christiaanb committed Nov 23, 2018
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