[euvm] Issue chipsalliance#778 fix, change mie behavior in setup_mmod…

…e_reg
coverify · Jan 9, 2024 · 8d3f233 · 8d3f233
1 parent f0a4179
commit 8d3f233
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/euvm/riscv/gen/riscv_privileged_common_seq.d b/euvm/riscv/gen/riscv_privileged_common_seq.d
@@ -146,7 +146,8 @@ class riscv_privileged_common_seq: uvm_sequence!(uvm_sequence_item,uvm_sequence_
     mstatus.set_field("SPP", 0);
     // Enable interrupt
     mstatus.set_field("MPIE", cfg.enable_interrupt);
-    mstatus.set_field("MIE", cfg.enable_interrupt);
+    // MIE is set when returning with mret, avoids trapping before returning
+    mstatus.set_field("MIE", 0);
     mstatus.set_field("SPIE", cfg.enable_interrupt);
     mstatus.set_field("SIE",  cfg.enable_interrupt);
     mstatus.set_field("UPIE", cfg.enable_interrupt);