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init_machine_mode code potentially triggers infinite loop. #778
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Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
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Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
vogelpi
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Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
vogelpi
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Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
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Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
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setup_mmode_reg(), called by enter_privileged_mode() in the gen_privileged_mode_switch_routine() enables the mstatus mie-flag and enables interrupts before mret is called. If an interrupt request is present when this flag is set, an infinite loop will occur:
Take the following example of generated code:
If an external interrupt is triggered at the mret instruction above, the return address for the trap (mepc) will be set to this mret. This will cause the final mret to return to itself, and end up in an infinite loop, as no further updates to mepc is performed.
From the Risc-V privileged spec:
Perhaps it is safer to not enable MIE directly, only MPIE in this code section, and let mret take care of enabling the exception when executing mret.
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