[RISC-V] fix rm field in riscvd instruction #101908
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Changed rm from 1 to 0. Fixed instructions: - fcvt.d.w - fcvt.w.d - fcvt.d.wu - fcvt.wu.d - fcvt.d.s - fcvt.s.d
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tomeksowi
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May 6, 2024
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Nit: s/riscvd/fcvt in title :) |
yurai007
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May 6, 2024
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michaelgsharp
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May 9, 2024
Changed rm from 1 to 0. Fixed instructions: - fcvt.d.w - fcvt.w.d - fcvt.d.wu - fcvt.wu.d - fcvt.d.s - fcvt.s.d
Ruihan-Yin
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May 30, 2024
Changed rm from 1 to 0. Fixed instructions: - fcvt.d.w - fcvt.w.d - fcvt.d.wu - fcvt.wu.d - fcvt.d.s - fcvt.s.d
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When i was working on #101683 I found that R2RDump prints
Decode Failurefor those instructions:, when i ran R2RDump e.g. for
System.Private.CoreLib.dll. I checked it is printed bylibcoredistoolsbecause LLVM MC cannot decode instructions properly. The problem is withrmfield. According to The RISC-V Instruction Set Manualand when i changed this field to 0 it fixed the problem. Below instructions also set
rmto 1I checked my changes running tests for coreclr with priority 1 and i didn't get any new error.
Part of #84834, cc @dotnet/samsung