Remove dead code in jit

src/coreclr/jit/codegen.h

@@ -1338,8 +1338,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     */
 
 public:
-    void instInit();
-
     void instGen(instruction ins);
 
     void inst_JMP(emitJumpKind jmp, BasicBlock* tgtBlock);
@@ -1384,10 +1382,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
         instruction ins, regNumber reg, target_ssize_t val, emitAttr size, insFlags flags = INS_FLAGS_DONT_CARE);
 
     void inst_ST_RV(instruction ins, TempDsc* tmp, unsigned ofs, regNumber reg, var_types type);
-    void inst_ST_IV(instruction ins, TempDsc* tmp, unsigned ofs, int val, var_types type);
-
-    void inst_SA_RV(instruction ins, unsigned ofs, regNumber reg, var_types type);
-    void inst_SA_IV(instruction ins, unsigned ofs, int val, var_types type);
 
     void inst_FS_ST(instruction ins, emitAttr size, TempDsc* tmp, unsigned ofs);
 
@@ -1402,54 +1396,28 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                     emitAttr    size  = EA_UNKNOWN,
                     insFlags    flags = INS_FLAGS_DONT_CARE);
 
-    void inst_FS_TT(instruction ins, GenTree* tree);
-
     void inst_RV_SH(instruction ins, emitAttr size, regNumber reg, unsigned val, insFlags flags = INS_FLAGS_DONT_CARE);
 
-    void inst_TT_SH(instruction ins, GenTree* tree, unsigned val, unsigned offs = 0);
-
-    void inst_RV_CL(instruction ins, regNumber reg, var_types type = TYP_I_IMPL);
-
-    void inst_TT_CL(instruction ins, GenTree* tree, unsigned offs = 0);
-
 #if defined(TARGET_XARCH)
     void inst_RV_RV_IV(instruction ins, emitAttr size, regNumber reg1, regNumber reg2, unsigned ival);
     void inst_RV_TT_IV(instruction ins, emitAttr attr, regNumber reg1, GenTree* rmOp, int ival);
     void inst_RV_RV_TT(instruction ins, emitAttr size, regNumber targetReg, regNumber op1Reg, GenTree* op2, bool isRMW);
 #endif
 
-    void inst_RV_RR(instruction ins, emitAttr size, regNumber reg1, regNumber reg2);
-
-    void inst_RV_ST(instruction ins, emitAttr size, regNumber reg, GenTree* tree);
-
-    void inst_mov_RV_ST(regNumber reg, GenTree* tree);
-
     void inst_set_SV_var(GenTree* tree);
 
 #ifdef TARGET_ARM
     bool arm_Valid_Imm_For_Instr(instruction ins, target_ssize_t imm, insFlags flags);
-    bool arm_Valid_Disp_For_LdSt(target_ssize_t disp, var_types type);
-    bool arm_Valid_Imm_For_Alu(target_ssize_t imm);
-    bool arm_Valid_Imm_For_Mov(target_ssize_t imm);
-    bool arm_Valid_Imm_For_Small_Mov(regNumber reg, target_ssize_t imm, insFlags flags);
     bool arm_Valid_Imm_For_Add(target_ssize_t imm, insFlags flag);
     bool arm_Valid_Imm_For_Add_SP(target_ssize_t imm);
-    bool arm_Valid_Imm_For_BL(ssize_t addr);
-
-    bool ins_Writes_Dest(instruction ins);
 #endif
 
-    bool isMoveIns(instruction ins);
     instruction ins_Move_Extend(var_types srcType, bool srcInReg);
 
     instruction ins_Copy(var_types dstType);
     instruction ins_Copy(regNumber srcReg, var_types dstType);
-    static instruction ins_FloatStore(var_types type = TYP_DOUBLE);
-    static instruction ins_FloatCopy(var_types type = TYP_DOUBLE);
     instruction ins_FloatConv(var_types to, var_types from);
-    instruction ins_FloatCompare(var_types type);
     instruction ins_MathOp(genTreeOps oper, var_types type);
-    instruction ins_FloatSqrt(var_types type);
 
     void instGen_Return(unsigned stkArgSize);
 
@@ -1469,16 +1437,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                                 insFlags flags = INS_FLAGS_DONT_CARE DEBUGARG(size_t targetHandle = 0)
                                     DEBUGARG(GenTreeFlags gtFlags = GTF_EMPTY));
 
-    void instGen_Compare_Reg_To_Zero(emitAttr size, regNumber reg);
-
-    void instGen_Compare_Reg_To_Reg(emitAttr size, regNumber reg1, regNumber reg2);
-
-    void instGen_Compare_Reg_To_Imm(emitAttr size, regNumber reg, target_ssize_t imm);
-
-    void instGen_Load_Reg_From_Lcl(var_types srcType, regNumber dstReg, int varNum, int offs);
-
-    void instGen_Store_Reg_Into_Lcl(var_types dstType, regNumber srcReg, int varNum, int offs);
-
 #ifdef TARGET_XARCH
     instruction genMapShiftInsToShiftByConstantIns(instruction ins, int shiftByValue);
 #endif // TARGET_XARCH
@@ -1528,45 +1486,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void inst_SETCC(GenCondition condition, var_types type, regNumber dstReg);
 };
 
-/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-XX                                                                           XX
-XX                       Instruction                                         XX
-XX                      Inline functions                                     XX
-XX                                                                           XX
-XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-*/
-
-#ifdef TARGET_XARCH
-/*****************************************************************************
- *
- *  Generate a floating-point instruction that has one operand given by
- *  a tree (which has been made addressable).
- */
-
-inline void CodeGen::inst_FS_TT(instruction ins, GenTree* tree)
-{
-    assert(instIsFP(ins));
-
-    assert(varTypeIsFloating(tree->gtType));
-
-    inst_TT(ins, tree, 0);
-}
-#endif
-
-/*****************************************************************************
- *
- *  Generate a "shift reg, cl" instruction.
- */
-
-inline void CodeGen::inst_RV_CL(instruction ins, regNumber reg, var_types type)
-{
-    inst_RV(ins, reg, type);
-}
-
-/*****************************************************************************/
-
 // A simple phase that just invokes a method on the codegen instance
 //
 class CodeGenPhase final : public Phase

src/coreclr/jit/codegenarm.cpp

@@ -182,7 +182,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr  size,
     {
         // TODO-CrossBitness: we wouldn't need the cast below if we had CodeGen::instGen_Set_Reg_To_Reloc_Imm.
         const int val32 = (int)imm;
-        if (arm_Valid_Imm_For_Mov(val32))
+        if (validImmForMov(val32))
         {
             GetEmitter()->emitIns_R_I(INS_mov, size, reg, val32, flags);
         }
@@ -191,7 +191,7 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr  size,
             const int imm_lo16 = val32 & 0xffff;
             const int imm_hi16 = (val32 >> 16) & 0xffff;
 
-            assert(arm_Valid_Imm_For_Mov(imm_lo16));
+            assert(validImmForMov(imm_lo16));
             assert(imm_hi16 != 0);
 
             GetEmitter()->emitIns_R_I(INS_movw, size, reg, imm_lo16);
@@ -1606,7 +1606,7 @@ void CodeGen::genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize,
         addr = compiler->compGetHelperFtn((CorInfoHelpFunc)helper, (void**)&pAddr);
     }
 
-    if (!addr || !arm_Valid_Imm_For_BL((ssize_t)addr))
+    if (!addr || !validImmForBL((ssize_t)addr))
     {
         if (callTargetReg == REG_NA)
         {

src/coreclr/jit/codegenarmarch.cpp

@@ -2582,7 +2582,7 @@ void CodeGen::genCallInstruction(GenTreeCall* call)
 
 // Non-virtual direct call to known addresses
 #ifdef TARGET_ARM
-            if (!arm_Valid_Imm_For_BL((ssize_t)addr))
+            if (!validImmForBL((ssize_t)addr))
             {
                 regNumber tmpReg = call->GetSingleTempReg();
                 instGen_Set_Reg_To_Imm(EA_HANDLE_CNS_RELOC, tmpReg, (ssize_t)addr);

src/coreclr/jit/codegencommon.cpp

@@ -100,8 +100,6 @@ CodeGen::CodeGen(Compiler* theCompiler) : CodeGenInterface(theCompiler)
 
     regSet.tmpInit();
 
-    instInit();
-
 #ifdef LATE_DISASM
     getDisAssembler().disInit(compiler);
 #endif

src/coreclr/jit/codegeninterface.h

@@ -310,7 +310,6 @@ class CodeGenInterface
     instruction ins_Load(var_types srcType, bool aligned = false);
     instruction ins_Store(var_types dstType, bool aligned = false);
     instruction ins_StoreFromSrc(regNumber srcReg, var_types dstType, bool aligned = false);
-    static instruction ins_FloatLoad(var_types type = TYP_DOUBLE);
 
     // Methods for spilling - used by RegSet
     void spillReg(var_types type, TempDsc* tmp, regNumber reg);

src/coreclr/jit/codegenxarch.cpp

@@ -4260,7 +4260,7 @@ void CodeGen::genCodeForShift(GenTree* tree)
         noway_assert(operandReg != REG_RCX);
 
         inst_Mov(targetType, tree->GetRegNum(), operandReg, /* canSkip */ true);
-        inst_RV_CL(ins, tree->GetRegNum(), targetType);
+        inst_RV(ins, tree->GetRegNum(), targetType);
     }
 
     genProduceReg(tree);
@@ -6083,7 +6083,7 @@ void CodeGen::genCompareFloat(GenTree* treeNode)
         std::swap(op1, op2);
     }
 
-    ins     = ins_FloatCompare(op1Type);
+    ins     = (op1Type == TYP_FLOAT) ? INS_ucomiss : INS_ucomisd;
     cmpAttr = emitTypeSize(op1Type);
 
     GetEmitter()->emitInsBinary(ins, cmpAttr, op1, op2);
@@ -7201,7 +7201,9 @@ void CodeGen::genIntrinsic(GenTree* treeNode)
             assert(srcNode->TypeGet() == treeNode->TypeGet());
 
             genConsumeOperands(treeNode->AsOp());
-            GetEmitter()->emitInsBinary(ins_FloatSqrt(treeNode->TypeGet()), emitTypeSize(treeNode), treeNode, srcNode);
+
+            const instruction ins = (treeNode->TypeGet() == TYP_FLOAT) ? INS_sqrtss : INS_sqrtsd;
+            GetEmitter()->emitInsBinary(ins, emitTypeSize(treeNode), treeNode, srcNode);
             break;
         }
 

src/coreclr/jit/emitarm.cpp

@@ -4801,7 +4801,7 @@ void emitter::emitIns_Call(EmitCallType          callType,
         assert(callType == EC_FUNC_TOKEN);
 
         // if addr is nullptr then this call is treated as a recursive call.
-        assert(addr == nullptr || codeGen->arm_Valid_Imm_For_BL((ssize_t)addr));
+        assert(addr == nullptr || codeGen->validImmForBL((ssize_t)addr));
 
         if (isJump)
         {