Allow constant propagation of Vector.Zero. #65028

TIHan · 2022-02-08T21:49:39Z

We need to merge #63821 first.

I did this work to gain some understanding of how value numbering and constant propagation work in the JIT.

Description

Example code:

    [MethodImpl(MethodImplOptions.NoInlining)]
    static Vector128<float> AdvSimd_CompareEqual_Vector128_Single_CreateZeroZeroZeroZero_AsVariable(Vector128<float> left)
    {
        var asVar = Vector128.Create(0f, 0f, 0f, 0f);
        return AdvSimd.CompareEqual(left, asVar);
    }

turns into:

    [MethodImpl(MethodImplOptions.NoInlining)]
    static Vector128<float> AdvSimd_CompareEqual_Vector128_Single_CreateZeroZeroZeroZero_AsVariable(Vector128<float> left)
    {
        return AdvSimd.CompareEqual(left, Vector128<float>.Zero);
    }

ARM64 diffs

 G_M36659_IG02:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
-            movi    v16.4s, #0x00
-            fcmeq   v16.4s, v0.4s, v16.4s
+            fcmeq   v16.4s, v0.4s, #0
             mov     v0.16b, v16.16b
-						;; bbWeight=1    PerfScore 2.00
+						;; bbWeight=1    PerfScore 1.50

 G_M303_IG02:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
-            movi    v16.4s, #0x00
             mov     w0, wzr
-						;; bbWeight=1    PerfScore 1.00
+						;; bbWeight=1    PerfScore 0.50
 G_M303_IG03:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz, align
-            fcmeq   v17.4s, v0.4s, v16.4s
+            fcmeq   v16.4s, v0.4s, #0
             mov     w1, wzr
             align   [4 bytes for IG04]
             align   [4 bytes]
+            align   [4 bytes]
             align   [0 bytes]
-            align   [0 bytes]
-						;; bbWeight=4    PerfScore 10.00
+						;; bbWeight=4    PerfScore 12.00
 G_M303_IG04:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, byref, isz
-            fcmeq   v17.4s, v0.4s, v16.4s
+            fcmeq   v16.4s, v0.4s, #0
             add     w1, w1, #1
             cmp     w1, #4
             blt     G_M303_IG04
@@ -43,14 +42,14 @@ G_M303_IG05:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
             blt     G_M303_IG03
 						;; bbWeight=4    PerfScore 8.00
 G_M303_IG06:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
-            mov     v0.16b, v17.16b
+            mov     v0.16b, v16.16b
 						;; bbWeight=1    PerfScore 0.50
 G_M303_IG07:        ; , epilog, nogc, extend
             ldp     fp, lr, [sp],#16
             ret     lr
 						;; bbWeight=1    PerfScore 2.00

 G_M7175_IG02:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
-            movi    v16.2d, #0x00
-            movi    v17.2d, #0x00
             mov     w0, wzr
-						;; bbWeight=1    PerfScore 1.50
+						;; bbWeight=1    PerfScore 0.50
 G_M7175_IG03:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz, align
-            cmeq    v18.2d, v0.2d, v17.2d
+            cmeq    v16.2d, v0.2d, #0
             mov     w1, wzr
             align   [4 bytes for IG04]
+            align   [4 bytes]
+            align   [4 bytes]
             align   [0 bytes]
-            align   [0 bytes]
-            align   [0 bytes]
-						;; bbWeight=4    PerfScore 8.00
+						;; bbWeight=4    PerfScore 12.00
 G_M7175_IG04:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, loop=IG04, byref, isz
-            cmeq    v18.2d, v0.2d, v16.2d
+            cmeq    v16.2d, v0.2d, #0
             add     w1, w1, #1
             cmp     w1, #4
             blt     G_M7175_IG04
@@ -45,14 +43,14 @@ G_M7175_IG05:        ; gcrefRegs=0000 {}, byrefRegs=0000 {}, byref, isz
             blt     G_M7175_IG03

Here are some notable x64 diffs:

 G_M3641_IG06:        ; gcrefRegs=00000008 {rbx}, byrefRegs=00000000 {}, byref
        vxorps   xmm6, xmm6, xmm6
        vxorps   xmm7, xmm7, xmm7
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
        call     hackishModuleName:hackishMethodName()
        ; gcr arg pop 0
        call     hackishModuleName:hackishMethodName()
@@ -443,8 +430,6 @@ G_M3641_IG06:        ; gcrefRegs=00000008 {rbx}, byrefRegs=00000000 {}, byref
        ; gcrRegs +[rax]
        ; gcr arg pop 0
        vmovupd  xmmword ptr [rax+8], xmm6

-G_M3641_IG08:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       jmp      SHORT G_M3641_IG10
-                        ;; bbWeight=0.50 PerfScore 2.17
-G_M3641_IG09:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
+       je       SHORT G_M3641_IG09
+                        ;; bbWeight=1    PerfScore 4.00
+G_M3641_IG08:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
        mov      esi, -1
                         ;; bbWeight=0.50 PerfScore 0.12
-G_M3641_IG10:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
+G_M3641_IG09:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
        mov      eax, esi

        call     CORINFO_HELP_ASSIGN_REF
        ; gcrRegs -[rdx rdi]
        ; byrRegs -[rcx]
-       vxorps   ymm0, ymm0, ymm0
        vmovupd  ymm6, ymmword ptr[reloc @RWD32]
-       vxorps   ymm0, ymm0, ymm0
        mov      rcx, 0xD1FFAB1E
        vextractf128 xmm7, ymm6, 1
        call     CORINFO_HELP_NEWSFAST
@@ -518,10 +516,10 @@ G_M50494_IG03:        ; , extend
        vmovupd  ymm0, ymmword ptr[reloc @RWD352]
        vmovupd  ymm1, ymmword ptr[reloc @RWD384]
        vmovupd  ymm2, ymmword ptr[reloc @RWD416]

Acceptance Criteria

Merge Morph Vector.Create(0) to Vector.Zero #63821
Add tests using loops

…arm64-opts1

src/coreclr/jit/valuenum.cpp

src/coreclr/jit/gentree.h

src/coreclr/jit/valuenum.cpp

jakobbotsch

LGTM with a few nits.

…reate-to-get_Zero

TIHan · 2022-02-18T19:51:23Z

Here are some notable x64 diffs:

 G_M3641_IG06:        ; gcrefRegs=00000008 {rbx}, byrefRegs=00000000 {}, byref
        vxorps   xmm6, xmm6, xmm6
        vxorps   xmm7, xmm7, xmm7
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
        call     hackishModuleName:hackishMethodName()
        ; gcr arg pop 0
        call     hackishModuleName:hackishMethodName()
@@ -443,8 +430,6 @@ G_M3641_IG06:        ; gcrefRegs=00000008 {rbx}, byrefRegs=00000000 {}, byref
        ; gcrRegs +[rax]
        ; gcr arg pop 0
        vmovupd  xmmword ptr [rax+8], xmm6

-G_M3641_IG08:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       vxorps   xmm0, xmm0, xmm0
-       jmp      SHORT G_M3641_IG10
-                        ;; bbWeight=0.50 PerfScore 2.17
-G_M3641_IG09:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
+       je       SHORT G_M3641_IG09
+                        ;; bbWeight=1    PerfScore 4.00
+G_M3641_IG08:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
        mov      esi, -1
                         ;; bbWeight=0.50 PerfScore 0.12
-G_M3641_IG10:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
+G_M3641_IG09:        ; gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref
        mov      eax, esi

        call     CORINFO_HELP_ASSIGN_REF
        ; gcrRegs -[rdx rdi]
        ; byrRegs -[rcx]
-       vxorps   ymm0, ymm0, ymm0
        vmovupd  ymm6, ymmword ptr[reloc @RWD32]
-       vxorps   ymm0, ymm0, ymm0
        mov      rcx, 0xD1FFAB1E
        vextractf128 xmm7, ymm6, 1
        call     CORINFO_HELP_NEWSFAST
@@ -518,10 +516,10 @@ G_M50494_IG03:        ; , extend
        vmovupd  ymm0, ymmword ptr[reloc @RWD352]
        vmovupd  ymm1, ymmword ptr[reloc @RWD384]
        vmovupd  ymm2, ymmword ptr[reloc @RWD416]

TIHan added 30 commits December 15, 2021 17:58

Initial work

7aca5dc

Added a comma to display

2752913

Cleanup

526e6c8

Fixing build

d850426

More cleanup

0ee6450

Update comment

cb5a82e

Update comment

6ae9a94

Added CompareEqual Vector64/128 with Zero tests

5c1997f

Merge remote-tracking branch 'upstream/main' into vector-64-128-zero-…

b33c72c

…arm64-opts1

Do not contain op1 for now

fd19fdc

Wrong intrinsic id used

178ff52

Removing generated tests

c0a23c0

Removing generated tests

ad780ea

Added CompareEqual tests

83c26ab

Supporting containment for first operand

9f7e7da

Fix test build

1e67415

Passing correct register

25b9d92

Check IsVectorZero before not allocing a register

c0dc7e4

Update comment

a718944

Fixing test

1f45fa2

Minor format change

cb872da

Fixed formatting

c0708d7

Renamed test

bf49d11

Adding AdvSimd_Arm64 tests:

bc7a557

Adding support for rest of 'cmeq' and 'fcmeq' instructions

5939f36

Removing github csproj

6cd0ea8

Minor test fix

2b30421

Fixed tests

0828de6

Fix print

fa43d19

Minor format change

911f929

TIHan added 2 commits February 11, 2022 11:33

Minor fix

bb58117

Minor comment update

7aae73b

SingleAccretion reviewed Feb 11, 2022

View reviewed changes

src/coreclr/jit/valuenum.cpp Outdated Show resolved Hide resolved

TIHan added 6 commits February 11, 2022 11:39

Added another comment

423d25a

Added another comment

616bb9b

Added another comment

84d3a94

Update comment

ac3b474

Formatting

2769740

Merge remote-tracking branch 'upstream/main' into vec-zero-vn

92df1fd

jakobbotsch reviewed Feb 14, 2022

View reviewed changes

src/coreclr/jit/gentree.h Outdated Show resolved Hide resolved

jakobbotsch reviewed Feb 14, 2022

View reviewed changes

src/coreclr/jit/valuenum.cpp Outdated Show resolved Hide resolved

jakobbotsch reviewed Feb 14, 2022

View reviewed changes

src/coreclr/jit/valuenum.cpp Outdated Show resolved Hide resolved

jakobbotsch reviewed Feb 14, 2022

View reviewed changes

JulieLeeMSFT requested a review from jakobbotsch February 14, 2022 14:58

JulieLeeMSFT added this to the 7.0.0 milestone Feb 14, 2022

runfoapp bot mentioned this pull request Feb 14, 2022

Failing test system.tests.gcextendedtests.getallocatedbytesforcurrentthread #65183

Closed

TIHan added 2 commits February 14, 2022 10:43

Feedback

4a6d9a2

Fixing build

2d6f367

jakobbotsch approved these changes Feb 15, 2022

View reviewed changes

TIHan mentioned this pull request Feb 15, 2022

Morph Vector.Create(0) to Vector.Zero #63821

Merged

4 tasks

TIHan added 6 commits February 15, 2022 17:32

Feedback

759e8c0

Merge remote-tracking branch 'upstream/main' into vector-64-128-256-C…

4c0f768

…reate-to-get_Zero

Merge branch 'vector-64-128-256-Create-to-get_Zero' into vec-zero-vn

1d7e408

Merging

0bdb08d

Update assertionprop.cpp

4bd81c7

Formatting

396e8a1

TIHan merged commit bdfff40 into dotnet:main Feb 18, 2022

TIHan deleted the vec-zero-vn branch February 18, 2022 19:51

ghost locked as resolved and limited conversation to collaborators Mar 21, 2022

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Allow constant propagation of Vector.Zero. #65028

Allow constant propagation of Vector.Zero. #65028

TIHan commented Feb 8, 2022 •

edited

Loading

jakobbotsch left a comment

TIHan commented Feb 18, 2022

Allow constant propagation of Vector.Zero. #65028

Allow constant propagation of Vector.Zero. #65028

Conversation

TIHan commented Feb 8, 2022 • edited Loading

jakobbotsch left a comment

Choose a reason for hiding this comment

TIHan commented Feb 18, 2022

TIHan commented Feb 8, 2022 •

edited

Loading