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Update project.tlv docs #73: Commit ed7a050 pushed by stevehoover
April 21, 2024 16:11 16s main
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April 21, 2024 16:11 16s
Update project.tlv test #10: Commit ed7a050 pushed by stevehoover
April 21, 2024 16:11 42s main
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April 21, 2024 16:11 42s
Update project.tlv fpga #74: Commit ed7a050 pushed by stevehoover
April 21, 2024 16:11 45s main
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April 21, 2024 16:11 45s
Update project.tlv gds #73: Commit ed7a050 pushed by stevehoover
April 21, 2024 16:11 18s main
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April 21, 2024 16:11 18s
Disabled tests and debugSigs. docs #72: Commit bd6c43c pushed by stevehoover
April 18, 2024 21:16 1m 14s main
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April 18, 2024 21:16 1m 14s
Disabled tests and debugSigs. gds #72: Commit bd6c43c pushed by stevehoover
April 18, 2024 21:16 3m 52s main
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April 18, 2024 21:16 3m 52s
Disabled tests and debugSigs. test #9: Commit bd6c43c pushed by stevehoover
April 18, 2024 21:16 35s main
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April 18, 2024 21:16 35s
Disabled tests and debugSigs. fpga #73: Commit bd6c43c pushed by stevehoover
April 18, 2024 21:16 43s main
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April 18, 2024 21:16 43s
Change from Verilog to SystemVerilog (from TL-Verilog). docs #71: Commit f620173 pushed by stevehoover
April 18, 2024 20:13 1m 11s main
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April 18, 2024 20:13 1m 11s
Change from Verilog to SystemVerilog (from TL-Verilog). fpga #72: Commit f620173 pushed by stevehoover
April 18, 2024 20:13 50s main
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April 18, 2024 20:13 50s
Change from Verilog to SystemVerilog (from TL-Verilog). test #8: Commit f620173 pushed by stevehoover
April 18, 2024 20:13 52s main
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April 18, 2024 20:13 52s
Change from Verilog to SystemVerilog (from TL-Verilog). gds #71: Commit f620173 pushed by stevehoover
April 18, 2024 20:13 3m 41s main
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April 18, 2024 20:13 3m 41s
Adding Verilog files to artifacts. test #7: Commit d850f3c pushed by stevehoover
April 18, 2024 19:33 30s main
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April 18, 2024 19:33 30s
Adding Verilog files to artifacts. docs #70: Commit d850f3c pushed by stevehoover
April 18, 2024 19:33 1m 13s main
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April 18, 2024 19:33 1m 13s
Adding Verilog files to artifacts. gds #70: Commit d850f3c pushed by stevehoover
April 18, 2024 19:33 3m 57s main
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April 18, 2024 19:33 3m 57s
Adding Verilog files to artifacts. fpga #71: Commit d850f3c pushed by stevehoover
April 18, 2024 19:33 44s main
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April 18, 2024 19:33 44s
Prepping source files. test #6: Commit afec985 pushed by stevehoover
April 17, 2024 22:00 35s main
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April 17, 2024 22:00 35s
Prepping source files. fpga #70: Commit afec985 pushed by stevehoover
April 17, 2024 22:00 42s main
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April 17, 2024 22:00 42s
Prepping source files. docs #69: Commit afec985 pushed by stevehoover
April 17, 2024 22:00 1m 9s main
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April 17, 2024 22:00 1m 9s
Prepping source files. gds #69: Commit afec985 pushed by stevehoover
April 17, 2024 22:00 3m 22s main
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April 17, 2024 22:00 3m 22s
Updated to be based on https://github.com/stevehoover/tt-fpga-hdl-demo, docs #68: Commit f0123bb pushed by stevehoover
April 17, 2024 21:20 1m 12s main
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April 17, 2024 21:20 1m 12s
Updated to be based on https://github.com/stevehoover/tt-fpga-hdl-demo, fpga #69: Commit f0123bb pushed by stevehoover
April 17, 2024 21:20 1m 0s main
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April 17, 2024 21:20 1m 0s
Updated to be based on https://github.com/stevehoover/tt-fpga-hdl-demo, gds #68: Commit f0123bb pushed by stevehoover
April 17, 2024 21:20 5m 16s main
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April 17, 2024 21:20 5m 16s
Updated to be based on https://github.com/stevehoover/tt-fpga-hdl-demo, test #5: Commit f0123bb pushed by stevehoover
April 17, 2024 21:20 33s main
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April 17, 2024 21:20 33s
update README.md test #4: Commit b094ebf pushed by jeffdi
February 4, 2024 02:56 36s main
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February 4, 2024 02:56 36s