Preliminary RISCV support #804
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This was referenced Jun 10, 2022
jessebraham
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@MabezDev LGTM, could you squash? |
- Add basic riscv32 executor - Add 16MHZ timer support
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huntc
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805: Preliminary Xtensa support r=Dirbaio a=MabezDev Based on the work in #804. I hope non-upstream target support is acceptable :). Co-authored-by: Scott Mabin <[email protected]>
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Moves the default Interrupt implementation into a cortex_m specific module(FYI esp implementation of embassy traits etc, is being developed here)
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