phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by u…

…sign it as PLL's feedback. TX: reduces PLL phase shift 90 -> 45

liteeth/phy/trionrgmii.py

@@ -144,9 +144,9 @@ def __init__(self, platform, clock_pads, with_hw_init_reset, hw_reset_cycles=256
         # -------
         self.pll = pll = TRIONPLL(platform)
         pll.register_clkin(None,          freq=125e6,           name=f"auto_eth{n}_rx_clk_in")
-        pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0,  name=f"auto_eth{n}_rx_clk", with_reset=False)
+        pll.create_clkout(self.cd_eth_rx, freq=125e6, phase=0, name=f"auto_eth{n}_rx_clk", with_reset=False, is_feedback=True)
         pll.create_clkout(self.cd_eth_tx, freq=125e6, phase=0,  name=f"auto_eth{n}_tx_clk", with_reset=False)
-        pll.create_clkout(None,           freq=125e6, phase=90, name=f"auto_eth{n}_tx_clk_delayed")
+        pll.create_clkout(None,           freq=125e6, phase=45, name=f"auto_eth{n}_tx_clk_delayed")
 
         # Reset.
         # ------