phy/s7pciephy: Allow updating tcl config from user design.

litepcie/phy/s7pciephy.py

@@ -72,6 +72,7 @@ def __init__(self, platform, pads, data_width=64,  cd="sys",
         self.max_request_size = Signal(16, reset_less=True)
         self.max_payload_size = Signal(16, reset_less=True)
 
+        self.config           = {}
         self.external_hard_ip = False
 
         # # #
@@ -444,7 +445,10 @@ def add_ltssm_tracer(self):
         self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm)
 
     # Hard IP sources ------------------------------------------------------------------------------
-    def add_sources(self, platform, phy_path, phy_filename=None):
+    def update_config(self, config):
+        self.config.update(config)
+
+    def add_sources(self, platform, phy_path, phy_filename=None, user_config=None):
         if phy_filename is not None:
             platform.add_ip(os.path.join(phy_path, phy_filename))
         else:
@@ -499,6 +503,9 @@ def add_sources(self, platform, phy_path, phy_filename=None):
                     "EXT_PCI_CFG_Space_Addr" : "6B", # 0x1AC.
                 })
 
+            # User/Custom Config.
+            config.update(self.config)
+
             # Tcl generation.
             ip_tcl = []
             ip_tcl.append("create_ip -vendor xilinx.com -name pcie_7x -module_name pcie_s7")