phy/us(p)pciephy: Add update_config support (similar to s7pciephy).

enjoy-digital · May 29, 2024 · 7ec8355 · 7ec8355
1 parent 5767a49
commit 7ec8355
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Showing 2 changed files with 18 additions and 0 deletions.
diff --git a/litepcie/phy/uspciephy.py b/litepcie/phy/uspciephy.py
@@ -80,6 +80,7 @@ def __init__(self, platform, pads, speed="gen3", data_width=64, cd="sys",
         self.max_request_size = Signal(16)
         self.max_payload_size = Signal(16)
 
+        self.config           = {}
         self.external_hard_ip = False
 
         # # #
@@ -370,6 +371,9 @@ def add_ltssm_tracer(self):
         self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm)
 
     # Hard IP sources ------------------------------------------------------------------------------
+    def update_config(self, config):
+        self.config.update(config)
+
     def add_sources(self, platform, phy_path=None, phy_filename=None):
         if phy_filename is not None:
             platform.add_ip(os.path.join(phy_path, phy_filename))
@@ -399,6 +403,11 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
                 # -----------------
                 "PF0_INTERRUPT_PIN"            : "NONE",
             }
+
+            # User/Custom Config.
+            config.update(self.config)
+
+            # Tcl generation.
             ip_tcl = []
             ip_tcl.append("create_ip -vendor xilinx.com -name pcie3_ultrascale -module_name pcie_us")
             ip_tcl.append("set obj [get_ips pcie_us]")

diff --git a/litepcie/phy/usppciephy.py b/litepcie/phy/usppciephy.py
@@ -85,6 +85,7 @@ def __init__(self, platform, pads, speed="gen3", data_width=64, cd="sys",
         self.max_request_size = Signal(16)
         self.max_payload_size = Signal(16)
 
+        self.config           = {}
         self.external_hard_ip = False
 
         # # #
@@ -375,6 +376,9 @@ def add_ltssm_tracer(self):
         self.ltssm_tracer = LTSSMTracer(self._link_status.fields.ltssm)
 
     # Hard IP sources ------------------------------------------------------------------------------
+    def update_config(self, config):
+        self.config.update(config)
+
     def add_sources(self, platform, phy_path=None, phy_filename=None):
         if phy_filename is not None:
             platform.add_ip(os.path.join(phy_path, phy_filename))
@@ -404,6 +408,11 @@ def add_sources(self, platform, phy_path=None, phy_filename=None):
                 # -----------------
                 "PF0_INTERRUPT_PIN"            : "NONE",
             }
+
+            # User/Custom Config.
+            config.update(self.config)
+
+            # Tcl generation.
             ip_tcl  = []
             ip_tcl.append(f"create_ip -vendor xilinx.com -name {self.ip_name} -module_name pcie_usp")
             ip_tcl.append("set obj [get_ips pcie_usp]")