Skip to content

Commit

Permalink
phy/s7pciephy: improve readability with aligning
Browse files Browse the repository at this point in the history
  • Loading branch information
@enjoy-digital
enjoy-digital committed Nov 4, 2019
1 parent a2fa870 commit dd57568
Showing 1 changed file with 71 additions and 71 deletions.
142 changes: 71 additions & 71 deletions litepcie/phy/s7pciephy.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,24 +15,24 @@
class S7PCIEPHY(Module, AutoCSR):
def __init__(self, platform, pads, data_width=64, bar0_size=1*MB, cd="sys"):
# Streams ----------------------------------------------------------------------------------
self.sink = stream.Endpoint(phy_layout(data_width))
self.sink = stream.Endpoint(phy_layout(data_width))
self.source = stream.Endpoint(phy_layout(data_width))
self.msi = stream.Endpoint(msi_layout())
self.msi = stream.Endpoint(msi_layout())

# Registers --------------------------------------------------------------------------------
self._lnk_up = CSRStatus()
self._msi_enable = CSRStatus()
self._lnk_up = CSRStatus()
self._msi_enable = CSRStatus()
self._bus_master_enable = CSRStatus()
self._max_request_size = CSRStatus(16)
self._max_payload_size = CSRStatus(16)
self._max_request_size = CSRStatus(16)
self._max_payload_size = CSRStatus(16)

# Parameters/Locals ------------------------------------------------------------------------
self.platform = platform
self.data_width = data_width
self.platform = platform
self.data_width = data_width

self.id = Signal(16)
self.bar0_size = bar0_size
self.bar0_mask = get_bar_mask(bar0_size)
self.id = Signal(16)
self.bar0_size = bar0_size
self.bar0_mask = get_bar_mask(bar0_size)
self.max_request_size = Signal(16)
self.max_payload_size = Signal(16)

Expand All @@ -56,8 +56,8 @@ def __init__(self, platform, pads, data_width=64, bar0_size=1*MB, cd="sys"):
else:
tx_buffer = stream.Buffer(phy_layout(data_width))
tx_buffer = ClockDomainsRenamer(cd)(tx_buffer)
tx_cdc = stream.AsyncFIFO(phy_layout(data_width), 4)
tx_cdc = ClockDomainsRenamer({"write": cd, "read": "pcie"})(tx_cdc)
tx_cdc = stream.AsyncFIFO(phy_layout(data_width), 4)
tx_cdc = ClockDomainsRenamer({"write": cd, "read": "pcie"})(tx_cdc)
self.submodules += tx_buffer, tx_cdc
self.comb += [
self.sink.connect(tx_buffer.sink),
Expand All @@ -69,8 +69,8 @@ def __init__(self, platform, pads, data_width=64, bar0_size=1*MB, cd="sys"):
if cd == "pcie":
m_axis_rx = self.source
else:
rx_cdc = stream.AsyncFIFO(phy_layout(data_width), 4)
rx_cdc = ClockDomainsRenamer({"write": "pcie", "read": cd})(rx_cdc)
rx_cdc = stream.AsyncFIFO(phy_layout(data_width), 4)
rx_cdc = ClockDomainsRenamer({"write": "pcie", "read": cd})(rx_cdc)
rx_buffer = stream.Buffer(phy_layout(data_width))
rx_buffer = ClockDomainsRenamer(cd)(rx_buffer)
self.submodules += rx_buffer, rx_cdc
Expand Down Expand Up @@ -99,13 +99,13 @@ def convert_size(command, size):
value = value*2
return Case(command, cases)

lnk_up = Signal()
msienable = Signal()
bus_number = Signal(8)
device_number = Signal(5)
lnk_up = Signal()
msienable = Signal()
bus_number = Signal(8)
device_number = Signal(5)
function_number = Signal(3)
command = Signal(16)
dcommand = Signal(16)
command = Signal(16)
dcommand = Signal(16)
self.sync.pcie += [
convert_size(dcommand[12:15], self.max_request_size),
convert_size(dcommand[5:8], self.max_payload_size),
Expand All @@ -123,58 +123,58 @@ def convert_size(command, size):
m_axis_rx_tlast = Signal()
m_axis_rx_tuser = Signal(32)
self.pcie_phy_params = dict(
p_C_DATA_WIDTH=data_width,
p_C_PCIE_GT_DEVICE={
p_C_DATA_WIDTH = data_width,
p_C_PCIE_GT_DEVICE = {
"xc7k": "GTX",
"xc7a": "GTP"}[platform.device[:4]],
p_C_BAR0=get_bar_mask(bar0_size),

i_sys_clk=pcie_refclk,
i_sys_rst_n=1 if not hasattr(pads, "rst_n") else pads.rst_n,

o_pci_exp_txp=pads.tx_p,
o_pci_exp_txn=pads.tx_n,

i_pci_exp_rxp=pads.rx_p,
i_pci_exp_rxn=pads.rx_n,

o_user_clk=ClockSignal("pcie"),
o_user_reset=ResetSignal("pcie"),
o_user_lnk_up=lnk_up,

#o_tx_buf_av=,
#o_tx_terr_drop=,
#o_tx_cfg_req=,
i_tx_cfg_gnt=1,

i_s_axis_tx_tvalid=s_axis_tx.valid,
i_s_axis_tx_tlast=s_axis_tx.last,
o_s_axis_tx_tready=s_axis_tx.ready,
i_s_axis_tx_tdata=s_axis_tx.dat,
i_s_axis_tx_tkeep=s_axis_tx.be,
i_s_axis_tx_tuser=0,

i_rx_np_ok=1,
i_rx_np_req=1,

o_m_axis_rx_tvalid=m_axis_rx.valid,
o_m_axis_rx_tlast=m_axis_rx_tlast,
i_m_axis_rx_tready=m_axis_rx.ready,
o_m_axis_rx_tdata=m_axis_rx.dat,
o_m_axis_rx_tkeep=m_axis_rx.be,
o_m_axis_rx_tuser=m_axis_rx_tuser,

#o_cfg_to_turnoff=,
o_cfg_bus_number=bus_number,
o_cfg_device_number=device_number,
o_cfg_function_number=function_number,
o_cfg_command=command,
o_cfg_dcommand=dcommand,
o_cfg_interrupt_msienable=msienable,

i_cfg_interrupt=cfg_msi.valid,
o_cfg_interrupt_rdy=cfg_msi.ready,
i_cfg_interrupt_di=cfg_msi.dat
p_C_BAR0 = get_bar_mask(bar0_size),

i_sys_clk = pcie_refclk,
i_sys_rst_n = 1 if not hasattr(pads, "rst_n") else pads.rst_n,

o_pci_exp_txp = pads.tx_p,
o_pci_exp_txn = pads.tx_n,

i_pci_exp_rxp = pads.rx_p,
i_pci_exp_rxn = pads.rx_n,

o_user_clk = ClockSignal("pcie"),
o_user_reset = ResetSignal("pcie"),
o_user_lnk_up = lnk_up,

#o_tx_buf_av = ,
#o_tx_terr_drop = ,
#o_tx_cfg_req = ,
i_tx_cfg_gnt = 1,

i_s_axis_tx_tvalid = s_axis_tx.valid,
i_s_axis_tx_tlast = s_axis_tx.last,
o_s_axis_tx_tready = s_axis_tx.ready,
i_s_axis_tx_tdata = s_axis_tx.dat,
i_s_axis_tx_tkeep = s_axis_tx.be,
i_s_axis_tx_tuser = 0,

i_rx_np_ok = 1,
i_rx_np_req = 1,

o_m_axis_rx_tvalid = m_axis_rx.valid,
o_m_axis_rx_tlast = m_axis_rx_tlast,
i_m_axis_rx_tready = m_axis_rx.ready,
o_m_axis_rx_tdata = m_axis_rx.dat,
o_m_axis_rx_tkeep = m_axis_rx.be,
o_m_axis_rx_tuser = m_axis_rx_tuser,

#o_cfg_to_turnoff = ,
o_cfg_bus_number = bus_number,
o_cfg_device_number = device_number,
o_cfg_function_number = function_number,
o_cfg_command = command,
o_cfg_dcommand = dcommand,
o_cfg_interrupt_msienable = msienable,

i_cfg_interrupt = cfg_msi.valid,
o_cfg_interrupt_rdy = cfg_msi.ready,
i_cfg_interrupt_di = cfg_msi.dat
)
if data_width == 128:
self.comb += m_axis_rx.last.eq(m_axis_rx_tuser[21])
Expand Down

0 comments on commit dd57568

Please sign in to comment.