[Issue-133] simcompare calculate signaltowidth instead of manual input

lib/src/utilities/simcompare.dart

@@ -147,24 +147,24 @@ abstract class SimCompare {
 
   /// Executes [vectors] against the Icarus Verilog simulator.
   static bool iverilogVector(
-    String generatedVerilog,
-    String topModule,
+    Module module,
     List<Vector> vectors, {
+    String? moduleName,
     bool dontDeleteTmpFiles = false,
     bool dumpWaves = false,
-    Map<String, int> signalToWidthMap = const {},
     List<String> iverilogExtraArgs = const [],
     bool allowWarnings = false,
   }) {
     String signalDeclaration(String signalName) {
-      if (signalToWidthMap.containsKey(signalName)) {
-        final width = signalToWidthMap[signalName]!;
-        return '[${width - 1}:0] $signalName';
+      final signal = module.signals.firstWhere((e) => e.name == signalName);
+      if (signal.width != 1) {
+        return '[${signal.width - 1}:0] $signalName';
       } else {
         return signalName;
       }
     }
 
+    final topModule = moduleName ?? module.definitionName;
     final allSignals = <String>{
       for (final e in vectors) ...e.inputValues.keys,
       for (final e in vectors) ...e.expectedOutputValues.keys,
@@ -174,6 +174,7 @@ abstract class SimCompare {
     final moduleConnections = allSignals.map((e) => '.$e($e)').join(', ');
     final moduleInstance = '$topModule dut($moduleConnections);';
     final stimulus = vectors.map((e) => e.toTbVerilog()).join('\n');
+    final generatedVerilog = module.generateSynth();
 
     // so that when they run in parallel, they dont step on each other
     final uniqueId =

test/assignment_test.dart

@@ -37,8 +37,7 @@ void main() {
     ];
     await SimCompare.checkFunctionalVector(exampleModule, vectors);
     final simResult = SimCompare.iverilogVector(
-      exampleModule.generateSynth(),
-      exampleModule.runtimeType.toString(),
+      exampleModule,
       vectors,
       allowWarnings: true, // since always_comb has no sensitivities
     );

test/bus_test.dart

@@ -270,51 +270,6 @@ void main() {
   });
 
   group('simcompare', () {
-    final signalToWidthMap = {
-      'a': 8,
-      'b': 8,
-      'a_bar': 8,
-      'a_and_b': 8,
-      'a_b_joined': 16,
-      'a_plus_b': 8,
-
-      // Slicing
-      'a_shrunk1': 3,
-      'a_shrunk2': 2,
-      'a_shrunk3': 1,
-      'a_neg_shrunk1': 3,
-      'a_neg_shrunk2': 2,
-      'a_neg_shrunk3': 1,
-      // Reverse Slicing
-      'a_rsliced1': 5,
-      'a_rsliced2': 2,
-      'a_rsliced3': 1,
-      'a_r_neg_sliced1': 5,
-      'a_r_neg_sliced2': 2,
-      'a_r_neg_sliced3': 1,
-
-      // getRange
-      'a_range1': 3,
-      'a_range2': 2,
-      'a_range3': 1,
-      'a_range4': 3,
-      'a_neg_range1': 3,
-      'a_neg_range2': 2,
-      'a_neg_range3': 1,
-      'a_neg_range4': 3,
-
-      // operator[]
-      'a_operator_indexing1': 1,
-      'a_operator_indexing2': 1,
-      'a_operator_indexing3': 1,
-      'a_operator_neg_indexing1': 1,
-      'a_operator_neg_indexing2': 1,
-      'a_operator_neg_indexing3': 1,
-
-      // Logic bus value Reversed
-      'a_reversed': 8,
-      'expression_bit_select': 4,
-    };
     test('NotGate bus', () async {
       final gtm = BusTestModule(Logic(width: 8), Logic(width: 8));
       await gtm.build();
@@ -325,9 +280,7 @@ void main() {
         Vector({'a': 1}, {'a_bar': 0xfe}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -343,9 +296,7 @@ void main() {
       ];
 
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -362,9 +313,7 @@ void main() {
       ];
 
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -401,9 +350,7 @@ void main() {
         Vector({'a': 0xba}, {'a_neg_shrunk3': 0})
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -440,9 +387,7 @@ void main() {
         Vector({'a': 0xaf}, {'a_r_neg_sliced3': 1})
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -455,9 +400,7 @@ void main() {
         Vector({'a': 0xf5}, {'a_reversed': 0xaf}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -502,9 +445,7 @@ void main() {
         Vector({'a': bin('11000101')}, {'a_neg_range4': bin('110')}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -519,9 +460,7 @@ void main() {
         Vector({'a': 0xaa, 'b': 0x55}, {'a_b_joined': 0x55aa}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -534,9 +473,7 @@ void main() {
         Vector({'a': 0xf5}, {'a1': 0}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -551,9 +488,7 @@ void main() {
         Vector({'a': 6, 'b': 7}, {'a_plus_b': 13}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
 
@@ -564,9 +499,7 @@ void main() {
         Vector({'a': 1, 'b': 1}, {'expression_bit_select': 2}),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
   });

test/collapse_test.dart

@@ -47,8 +47,7 @@ void main() {
       Vector({'a': 0, 'b': 0}, {'c': 0, 'd': 0, 'e': 0, 'f': 0}),
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors);
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 

test/comb_math_test.dart

@@ -127,9 +127,7 @@ void main() {
 
     await SimCompare.checkFunctionalVector(mod, vectors);
 
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'codepoint': 21, 'bytes': 32});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 
@@ -146,9 +144,7 @@ void main() {
     }
 
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'codepoint': 21, 'bytes': 32});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 
@@ -161,9 +157,7 @@ void main() {
       Vector({'a': 0xff}, {'b': bin('00001111')})
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 
@@ -176,9 +170,7 @@ void main() {
       Vector({'a': 0xff}, {'b': bin('00001111')})
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 
@@ -191,9 +183,7 @@ void main() {
       Vector({'a': 0xff}, {'b': bin('00001111')})
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 }

test/comb_mod_test.dart

@@ -68,9 +68,7 @@ void main() {
       Vector({'a': 3}, {'b': 5})
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 
@@ -82,9 +80,7 @@ void main() {
       Vector({'a': 3}, {'b': 5})
     ];
     await SimCompare.checkFunctionalVector(mod, vectors);
-    final simResult = SimCompare.iverilogVector(
-        mod.generateSynth(), mod.runtimeType.toString(), vectors,
-        signalToWidthMap: {'a': 8, 'b': 8});
+    final simResult = SimCompare.iverilogVector(mod, vectors);
     expect(simResult, equals(true));
   });
 }

test/comparison_test.dart

@@ -51,11 +51,6 @@ void main() {
   tearDown(Simulator.reset);
 
   group('simcompare', () {
-    final signalToWidthMap = {
-      'a': 8,
-      'b': 8,
-    };
-
     test('compares', () async {
       final gtm = ComparisonTestModule(Logic(width: 8), Logic(width: 8));
       await gtm.build();
@@ -107,9 +102,7 @@ void main() {
         }),
       ];
       await SimCompare.checkFunctionalVector(gtm, vectors);
-      final simResult = SimCompare.iverilogVector(
-          gtm.generateSynth(), gtm.runtimeType.toString(), vectors,
-          signalToWidthMap: signalToWidthMap);
+      final simResult = SimCompare.iverilogVector(gtm, vectors);
       expect(simResult, equals(true));
     });
   });