Update google_riscv-dv to chipsalliance/riscv-dv@ea8dd25

Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
lowRISC · Dec 3, 2021 · d8e50dc · d8e50dc
1 parent 169785d
commit d8e50dc
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Showing 62 changed files with 3,993 additions and 1,562 deletions.
diff --git a/dv/uvm/core_ibex/Makefile b/dv/uvm/core_ibex/Makefile
@@ -51,7 +51,14 @@ ISS                 := spike
 # ISS runtime options
 ISS_OPTS            :=
 # ISA
-ISA                 := rv32imcb
+# Both an updated compiler and ISS are required to verify the bitmanip v.1.00
+# and draft v.0.93 extensions. For now, disable the bitmanip tests and verify
+# RV32IMC only.
+# For details, refer to https://github.com/lowRISC/ibex/issues/1470
+#ISA                 := rv32imcb
+#ISA_ISS             := rv32imc_Zba_Zbb_Zbc_Zbs_Xbitmanip
+ISA                 := rv32imc
+ISA_ISS             := rv32imc
 # Test name (default: full regression)
 TEST                := all
 TESTLIST            := riscv_dv_extension/testlist.yaml
@@ -125,7 +132,6 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
          --end_signature_addr=${SIGNATURE_ADDR}
 
 RISCV_DV_OPTS=--custom_target=riscv_dv_extension \
-              --isa="${ISA}" \
               --mabi=ilp32 \
 
 # To avoid cluttering the output directory with stamp files, we place them in
@@ -244,7 +250,7 @@ tests-and-seeds := \
 #
 # To do this variable tracking, we dump each of the variables to a Makefile
 # fragment and try to load it up the next time around.
-gen-var-deps := GEN_OPTS SIMULATOR RISCV_DV_OPTS CSR_OPTS \
+gen-var-deps := GEN_OPTS SIMULATOR RISCV_DV_OPTS ISA CSR_OPTS \
 	            SIGNATURE_ADDR PMP_REGIONS PMP_GRANULARITY TEST_OPTS
 
 # Load up the generation stage's saved variable values. If this fails, that's
@@ -281,6 +287,7 @@ $(metadata)/instr_gen.gen.stamp: \
      --lsf_cmd="${LSF_CMD}" \
      --simulator="${SIMULATOR}" \
      ${RISCV_DV_OPTS} \
+     --isa=${ISA} \
      ${TEST_OPTS} \
      ${CSR_OPTS} \
      --sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
@@ -304,7 +311,8 @@ $(metadata)/instr_gen.compile.stamp: \
      --steps=gcc_compile \
      ${TEST_OPTS} \
      --gcc_opts=-mno-strict-align \
-     ${RISCV_DV_OPTS} && \
+     ${RISCV_DV_OPTS} \
+     --isa=${ISA} && \
 	  touch $@
 
 .PHONY: gcc_compile
@@ -329,7 +337,7 @@ $(metadata)/instr_gen.iss.stamp: \
      ${TEST_OPTS} \
      --iss="${ISS}" \
      --iss_opts="${ISS_OPTS}" \
-     --isa="${ISA}" \
+     --isa="${ISA_ISS}" \
      ${RISCV_DV_OPTS}
 	$(call dump-vars,$(metadata)/iss-vars.mk,iss,$(iss-var-deps))
 	@touch $@

diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.sv
@@ -52,7 +52,8 @@ riscv_instr_name_t unsupported_instr[] = {FENCE_I};
 bit support_unaligned_load_store = 1'b1;
 
 // ISA supported by the processor
-riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C, RV32B};
+riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C,
+    RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS, RV32B};
 
 // Interrupt mode support
 mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};

diff --git a/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml b/dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
@@ -715,28 +715,41 @@
 
   # Disable cosim for bitmanip tests for now as Ibex implements a different
   # version of the spec compared to the Spike version used for the cosim.
-- test: riscv_bitmanip_full_test
-  desc: >
-    Random instruction test with supported B extension instructions in full configuration
-  iterations: 10
-  gen_test: riscv_rand_instr_test
-  gen_opts: >
-    +enable_b_extension=1
-    +enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbp,zbf,zbe,zbc,zbr
-    +disable_cosim=1
-  rtl_test: core_ibex_base_test
-  rtl_params:
-    RV32B: "ibex_pkg::RV32BFull"
 
-- test: riscv_bitmanip_balanced_test
-  desc: >
-    Random instruction test with supported B extension instructions in balanced configuration
-  iterations: 10
-  gen_test: riscv_rand_instr_test
-  gen_opts: >
-    +enable_b_extension=1
-    +enable_bitmanip_groups=zbb,zb_tmp,zbt,zbs,zbf
-    +disable_cosim=1
-  rtl_test: core_ibex_base_test
-  rtl_params:
-    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BBalanced"]
+# Both an updated compiler and ISS are required to verify the bitmanip v.1.00
+# and draft v.0.93 extensions. For now, disable the bitmanip tests.
+# For details, refer to https://github.com/lowRISC/ibex/issues/1470
+#ISA                 := rv32imcb
+#ISA_ISS             := rv32imc_Zba_Zbb_Zbc_Zbs_Xbitmanip
+#- test: riscv_bitmanip_full_test
+#  desc: >
+#    Random instruction test with supported B extension instructions in full configuration
+#  iterations: 10
+#  gen_test: riscv_rand_instr_test
+#  gen_opts: >
+#    +enable_zba_extension=1
+#    +enable_zbb_extension=1
+#    +enable_zbc_extension=1
+#    +enable_zbs_extension=1
+#    +enable_b_extension=1
+#    +enable_bitmanip_groups=zbe,zbf,zbp,zbr,zbt
+#    +disable_cosim=1
+#  rtl_test: core_ibex_base_test
+#  rtl_params:
+#    RV32B: "ibex_pkg::RV32BFull"
+#
+#- test: riscv_bitmanip_balanced_test
+#  desc: >
+#    Random instruction test with supported B extension instructions in balanced configuration
+#  iterations: 10
+#  gen_test: riscv_rand_instr_test
+#  gen_opts: >
+#    +enable_zba_extension=1
+#    +enable_zbb_extension=1
+#    +enable_zbs_extension=1
+#    +enable_b_extension=1
+#    +enable_bitmanip_groups=zbf,zbt
+#    +disable_cosim=1
+#  rtl_test: core_ibex_base_test
+#  rtl_params:
+#    RV32B: ["ibex_pkg::RV32BFull", "ibex_pkg::RV32BBalanced"]
diff --git a/vendor/google_riscv-dv.lock.hjson b/vendor/google_riscv-dv.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/google/riscv-dv
-    rev: 59dcd8c813484eb6dcca67e7e36089fe772b9cc8
+    rev: ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0
   }
 }
diff --git a/vendor/google_riscv-dv/pygen/pygen_src/README.md b/vendor/google_riscv-dv/pygen/pygen_src/README.md
@@ -0,0 +1,99 @@
+## Overview
+
+RISCV-DV-PyFlow is a purely Python based open-source instruction generator for RISC-V processor
+verification. It uses [PyVSC](https://github.com/fvutils/pyvsc) as the main library for
+randomization and coverage collection. It currently supports the following features:
+
+- Supported instruction set: RV32IMAFDC
+- Supported privileged modes: For now only machine mode is supported.
+- Illegal instruction and HINT instruction generation
+- Random forward/backward branch instructions
+- Supports mixing directed instructions with random instruction stream
+- Support for direct & vectored interrupt table.
+- Multi-hart support
+- Functional coverage framework (reports GUI as well as text, currently
+  supports RV32IMFDC extensions)
+- Supported ISS : Spike, OVPsim
+
+## Supported tests
+
+- riscv_arithmetic_basic_test
+- riscv_amo_test
+- riscv_floating_point_arithmetic_test
+- riscv_floating_point_rand_test
+- riscv_floating_point_mmu_stress_test
+- riscv_b_ext_test
+- riscv_rand_instr_test
+- riscv_jump_stress_test
+- riscv_rand_jump_test
+- riscv_mmu_stress_test
+- riscv_illegal_instr_test
+- riscv_unaligned_load_store_test
+- riscv_single_hart_test
+- riscv_non_compressed_instr_test
+- riscv_loop_test
+
+
+## Getting Started
+
+### Prerequisites
+
+To be able to run the generator, you need to have RISCV-GCC compiler toolchain and ISS
+(Instruction Set Simulator) installed (Spike is preferred).
+
+
+### Install RISCV-DV-PyFlow
+
+Getting the source
+```bash
+git clone https://github.com/google/riscv-dv.git
+```
+
+```bash
+pip3 install -r requirements.txt    # install dependencies (only once)
+python3 run.py --help
+```
+
+## Running the Generator
+
+Command to run a single test:
+```bash
+python3 run.py --test=riscv_arithmetic_basic_test --simulator=pyflow
+```
+--simulator=pyflow will invoke the Python generator.
+
+Run a single test 10 times
+```bash
+python3 run.py --test=riscv_arithmetic_basic_test --iterations=10 --simulator=pyflow
+```
+Run the generator only, do not compile and simluation with ISS
+```bash
+python3 run.py --test=riscv_arithmetic_basic_test --simulator=pyflow --steps gen
+```
+## Coverage Model
+The coverage model of PyFlow is developed using PyVSC library.
+
+Command to generate the coverage report.
+#### Process spike simulation log and collect functional coverage
+```bash
+python3 cov.py --dir out/spike_sim/ --simulator=pyflow --enable_visualization
+```
+--enable_visualization helps enabling coverage report visualization for pyflow.
+#### Get the command reference
+```bash
+cov --help
+```
+#### Run the coverage flow with predefined targets
+```bash
+python3 cov.py --dir out/spike_sim/ --simulator=pyflow --enable_visualization --target rv32imc
+```
+The coverage reports can be viewed using two ways:
+1) Text format: By opening the CoverageReport.txt file.
+2) GUI format: By opening the cov_db.xml using pyucis-viewer.
+The GUI format could be enabled using "--enable_visualization" command option.
+```bash
+pyucis-viewer cov_db.xml
+```
+## Note
+Currently, time to generate a single program with larger than 10k instructions is around
+12 minutes. We are working on improving the overall performance.
diff --git a/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_compressed_instr.py b/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_compressed_instr.py
@@ -223,6 +223,6 @@ def conver2bin(self, prefix=""):
     def get_c_opcode(self):
         pass
 
-    # TOD0
+    # TODO
     def get_func3(self):
         pass
diff --git a/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_cov_instr.py b/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_cov_instr.py
@@ -19,11 +19,11 @@
 import logging
 from importlib import import_module
 from enum import Enum, IntEnum, auto
-from bitstring import BitArray
 from pygen_src.riscv_instr_pkg import *
 from pygen_src.riscv_instr_gen_config import cfg
 rcs = import_module("pygen_src.target." + cfg.argv.target + ".riscv_core_setting")
 
+
 class operand_sign_e(IntEnum):
     POSITIVE = 0
     NEGATIVE = auto()
@@ -35,6 +35,11 @@ class div_result_e(IntEnum):
     DIV_OVERFLOW = auto()
 
 
+class div_result_ex_overflow_e(IntEnum):
+    DIV_NORMAL = 0
+    DIV_BY_ZERO = auto()
+
+
 class compare_result_e(IntEnum):
     EQUAL = 0
     LARGER = auto()
@@ -142,7 +147,7 @@ def set_imm_len(self):
             if self.imm_type.name == "UIMM":
                 self.imm_len = 5
             else:
-                self.imm_len = 11
+                self.imm_len = 12
 
     def set_mode(self):
         # mode setting for Instruction Format
@@ -320,10 +325,11 @@ def check_hazard_condition(self, pre_instr):
         the result of the check_hazard_condition won't be accurate. Need to
         explicitly extract the destination register from the operands '''
         if pre_instr.has_rd:
-            if ((self.has_rs1 and self.rs1 == pre_instr.rd) or
-                    (self.has_rs2 and self.rs1 == pre_instr.rd)):
+            if ((self.has_rs1 and (self.rs1 == pre_instr.rd)) or
+                    (self.has_rs2 and (self.rs1 == pre_instr.rd))):
+                logging.info("pre_instr {}".format(pre_instr.instr.name))
                 self.gpr_hazard = hazard_e["RAW_HAZARD"]
-            elif self.has_rd and self.rd == pre_instr.rd:
+            elif self.has_rd and (self.rd == pre_instr.rd):
                 self.gpr_hazard = hazard_e["WAW_HAZARD"]
             elif (self.has_rd and
                   ((pre_instr.has_rs1 and (pre_instr.rs1 == self.rd)) or
@@ -333,16 +339,16 @@ def check_hazard_condition(self, pre_instr):
                 self.gpr_hazard = hazard_e["NO_HAZARD"]
         if self.category == riscv_instr_category_t.LOAD:
             if (pre_instr.category == riscv_instr_category_t.STORE and
-                    pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
+                    (pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
                 self.lsu_hazard = hazard_e["RAW_HAZARD"]
             else:
                 self.lsu_hazard = hazard_e["NO_HAZARD"]
         if self.category == riscv_instr_category_t.STORE:
             if (pre_instr.category == riscv_instr_category_t.STORE and
-                    pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
+                    (pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
                 self.lsu_hazard = hazard_e["WAW_HAZARD"]
             elif (pre_instr.category == riscv_instr_category_t.LOAD and
-                  pre_instr.mem_addr.get_val() == self.mem_addr.get_val()):
+                  (pre_instr.mem_addr.get_val() == self.mem_addr.get_val())):
                 self.lsu_hazard = hazard_e["WAR_HAZARD"]
             else:
                 self.lsu_hazard = hazard_e["NO_HAZARD"]

diff --git a/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_floating_point_instr.py b/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_floating_point_instr.py
@@ -116,7 +116,7 @@ def set_rand_mode(self):
             self.has_fs1 = 0
             self.has_fd = 0
         else:
-            logging.info("Unsupported format %0s", self.format.name)
+            logging.info("Unsupported format {}".format(self.format.name))
 
     def pre_randomize(self):
         super().pre_randomize()

diff --git a/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_instr.py b/vendor/google_riscv-dv/pygen/pygen_src/isa/riscv_instr.py
@@ -1,15 +1,13 @@
 """
 Copyright 2020 Google LLC
 Copyright 2020 PerfectVIPs Inc.
-
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 http://www.apache.org/licenses/LICENSE-2.0
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-
 """
 
 import logging
@@ -110,12 +108,32 @@ def imm_c(self):
             with vsc.if_then(self.XLEN != 32):
                 self.imm[11:6] == 0
 
+    @vsc.constraint
+    def csr_c(self):
+        # TODO
+        pass
+
     @classmethod
     def register(cls, instr_name, instr_group):
         logging.info("Registering {}".format(instr_name.name))
         cls.instr_registry[instr_name] = instr_group
         return 1
 
+    def __deepcopy__(self, memo):
+        cls = self.__class__  # Extract the class of the object.
+        # Create a new instance of the object based on extracted class.
+        result = cls.__new__(cls)
+        memo[id(self)] = result
+        for k, v in self.__dict__.items():
+            if k in ["_ro_int", "tname", "__field_info"]:
+                continue  # Skip the fields which are not required.
+            else:
+                # Copy over attributes by copying directly.
+                setattr(result, k, copy.deepcopy(v, memo))
+        return result
+
+    # Create the list of instructions based on the supported ISA extensions and configuration
+    # of the generator
     @classmethod
     def create_instr_list(cls, cfg):
         cls.instr_names.clear()
@@ -129,6 +147,7 @@ def create_instr_list(cls, cfg):
 
             if not instr_inst.is_supported(cfg):
                 continue
+            # C_JAL is RV32C only instruction
             if ((rcs.XLEN != 32) and (instr_name == riscv_instr_name_t.C_JAL)):
                 continue
             if ((riscv_reg_t.SP in cfg.reserved_regs) and
@@ -310,7 +329,7 @@ def set_imm_len(self):
             if self.imm_type.name == "UIMM":
                 self.imm_len = 5
             else:
-                self.imm_len = 11
+                self.imm_len = 12
         self.imm_mask = (self.imm_mask << self.imm_len) & self.shift_t
 
     def extend_imm(self):