[darjeeling] Instantiate Darjeeling on master

hw/Makefile

@@ -46,7 +46,7 @@ IPS ?= aes           \
        uart          \
        usbdev
 
-TOPS ?= top_earlgrey
+TOPS ?= top_darjeeling top_earlgrey
 
 USE_BUFFER ?= 0
 

hw/ip/keymgr/keymgr_common.core

@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:ip:keymgr_common:0.1"
+description: "Keymgr modules that are also used in Keymgr_DPE"
+
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:edn_req
+      - lowrisc:ip:keymgr_pkg
+      - lowrisc:ip:kmac_pkg
+    files:
+      - rtl/keymgr_cfg_en.sv
+      - rtl/keymgr_reseed_ctrl.sv
+      - rtl/keymgr_sideload_key.sv
+      - rtl/keymgr_sideload_key_ctrl.sv
+      - rtl/keymgr_data_en_state.sv
+      - rtl/keymgr_kmac_if.sv
+      - rtl/keymgr_input_checks.sv
+      - rtl/keymgr_err.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl

hw/ip_templates/pinmux/data/pinmux.hjson.tpl

@@ -399,6 +399,7 @@
     { name: "BUS.INTEGRITY",
       desc: "End-to-end bus integrity scheme."
     }
+  % if enable_strap_sampling:
     { name: "LC_DFT_EN.INTERSIG.MUBI",
       desc: "The life cycle DFT enable signal is multibit encoded."
     }
@@ -425,6 +426,7 @@
                the DFT TAP can only be selected when LC_DFT_EN is asserted.
             '''
     }
+  % endif
   ]
 
   registers: [

hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson → hw/ip_templates/pinmux/data/pinmux_sec_cm_testplan.hjson.tpl

@@ -29,6 +29,7 @@
       stage: V2S
       tests: []
     }
+  % if enable_strap_sampling:
     {
       name: sec_cm_lc_dft_en_intersig_mubi
       desc: "Verify the countermeasure(s) LC_DFT_EN.INTERSIG.MUBI."
@@ -65,5 +66,6 @@
       stage: V2S
       tests: []
     }
+  % endif
   ]
 }

hw/ip_templates/pinmux/pinmux.core.tpl

@@ -28,7 +28,9 @@ filesets:
       - rtl/pinmux_wkup.sv
       - rtl/pinmux_jtag_buf.sv
       - rtl/pinmux_jtag_breakout.sv
+    % if enable_strap_sampling:
       - rtl/pinmux_strap_sampling.sv
+    % endif
       - rtl/pinmux.sv
     file_type: systemVerilogSource
 

hw/ip_templates/pinmux/rtl/pinmux.sv.tpl

@@ -298,6 +298,10 @@ module pinmux
     assign hw2reg.mio_pad_attr[k].invert.d         = mio_attr[k].invert;
   end
 
+  // Local versions of the input signals
+  logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
+  logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
+
 % if enable_strap_sampling:
 
   //////////////////////////
@@ -338,10 +342,6 @@ module pinmux
     assign strap_en = strap_en_i;
   end
 
-  // Local versions of the input signals
-  logic [NMioPads-1:0] mio_out, mio_oe, mio_in;
-  logic [NDioPads-1:0] dio_out, dio_oe, dio_in;
-
   // This module contains the strap sampling and JTAG mux.
   // Affected inputs are intercepted/tapped before they go to the pinmux
   // matrix. Likewise, affected outputs are intercepted/tapped after the