Wrong instruction fetch caused by multicycle F instructions | Forwarding issue #722
Labels
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
PARAM:FPU
Issue depends on the FPU parameter
Status:Resolved
Issue has been resolved, but closure is pending on git merge and/or issuer confirmation
Type:Bug
For bugs in the RTL, Documentation, Verification environment or Tool and Build system
Issue Description
Jump instructions set the wrong PC in case they are preceded by a multicycle F instruction and their source register is the same destination register of the floating point one.
Component
Component:RTL
RISC-V Specification
Steps to Reproduce
As shown below, the following sequence of instructions happens:
The first instruction updates
x8
register (Zfinx
is set) with the value32'h7fc00000
(NaN
result of division by 0). Whenjalr
instruction is executed, it sets the PC wrongly to32'hffffffc2
, which is the value of adding the immediate32'hffffff8d
to the old content32'h36
ofx8
. The correct PC should be32'h7fbfff8c
, resulting from adding the immediate32'hffffff8d
to the new content32'h7fc00000
ofx8
.Top Level Parameters
Git Hash: d0d1c25
Flist: cv32e40p_fpu_manifest.flist
VCD: bug_1.vcd
Product: OneSpin 360 DV-Verify
App: Processor Verification App
Tool's version: 2022.3_1
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