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Issue openhwgroup#722 correction.
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Signed-off-by: Pascal Gouedo <[email protected]>
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Pascal Gouedo committed Aug 29, 2023
1 parent a820cfa commit e4374ab
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Showing 5 changed files with 74 additions and 50 deletions.
5 changes: 5 additions & 0 deletions rtl/cv32e40p_apu_disp.sv
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Expand Up @@ -47,6 +47,7 @@ module cv32e40p_apu_disp (
input logic [2:0][5:0] read_regs_i,
input logic [2:0] read_regs_valid_i,
output logic read_dep_o,
output logic read_dep_for_jalr_o,

input logic [1:0][5:0] write_regs_i,
input logic [1:0] write_regs_valid_i,
Expand Down Expand Up @@ -189,6 +190,10 @@ module cv32e40p_apu_disp (
assign read_dep_o = (read_dep_req | read_dep_inflight | read_dep_waiting) & is_decoding_i;
assign write_dep_o = (write_dep_req | write_dep_inflight | write_dep_waiting) & is_decoding_i;

assign read_dep_for_jalr_o = is_decoding_i & ((|read_deps_req & enable_i) |
(|read_deps_inflight & valid_inflight) |
(|read_deps_waiting & valid_waiting));

//
// Stall signals
//
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9 changes: 7 additions & 2 deletions rtl/cv32e40p_controller.sv
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Expand Up @@ -31,7 +31,8 @@
module cv32e40p_controller import cv32e40p_pkg::*;
#(
parameter COREV_CLUSTER = 0,
parameter COREV_PULP = 1
parameter COREV_PULP = 0,
parameter FPU = 0
)
(
input logic clk, // Gated clock
Expand Down Expand Up @@ -104,6 +105,7 @@ module cv32e40p_controller import cv32e40p_pkg::*;
// APU dependency checks
input logic apu_en_i,
input logic apu_read_dep_i,
input logic apu_read_dep_for_jalr_i,
input logic apu_write_dep_i,

output logic apu_stall_o,
Expand Down Expand Up @@ -1338,7 +1340,10 @@ endgenerate
if ((ctrl_transfer_insn_in_dec_i == BRANCH_JALR) &&
(((regfile_we_wb_i == 1'b1) && (reg_d_wb_is_reg_a_i == 1'b1)) ||
((regfile_we_ex_i == 1'b1) && (reg_d_ex_is_reg_a_i == 1'b1)) ||
((regfile_alu_we_fw_i == 1'b1) && (reg_d_alu_is_reg_a_i == 1'b1))) )
((regfile_alu_we_fw_i == 1'b1) && (reg_d_alu_is_reg_a_i == 1'b1)) ||
(FPU && (apu_read_dep_for_jalr_i == 1'b1))
)
)
begin
jr_stall_o = 1'b1;
deassert_we_o = 1'b1;
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31 changes: 17 additions & 14 deletions rtl/cv32e40p_core.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,7 @@ module cv32e40p_core
logic [ 2:0][ 5:0] apu_read_regs;
logic [ 2:0] apu_read_regs_valid;
logic apu_read_dep;
logic apu_read_dep_for_jalr;
logic [ 1:0][ 5:0] apu_write_regs;
logic [ 1:0] apu_write_regs_valid;
logic apu_write_dep;
Expand Down Expand Up @@ -620,14 +621,15 @@ module cv32e40p_core
.apu_flags_ex_o (apu_flags_ex),
.apu_waddr_ex_o (apu_waddr_ex),

.apu_read_regs_o (apu_read_regs),
.apu_read_regs_valid_o (apu_read_regs_valid),
.apu_read_dep_i (apu_read_dep),
.apu_write_regs_o (apu_write_regs),
.apu_write_regs_valid_o(apu_write_regs_valid),
.apu_write_dep_i (apu_write_dep),
.apu_perf_dep_o (perf_apu_dep),
.apu_busy_i (apu_busy),
.apu_read_regs_o (apu_read_regs),
.apu_read_regs_valid_o (apu_read_regs_valid),
.apu_read_dep_i (apu_read_dep),
.apu_read_dep_for_jalr_i(apu_read_dep_for_jalr),
.apu_write_regs_o (apu_write_regs),
.apu_write_regs_valid_o (apu_write_regs_valid),
.apu_write_dep_i (apu_write_dep),
.apu_perf_dep_o (perf_apu_dep),
.apu_busy_i (apu_busy),

// CSR ID/EX
.csr_access_ex_o (csr_access_ex),
Expand Down Expand Up @@ -792,12 +794,13 @@ module cv32e40p_core
.apu_operands_i(apu_operands_ex),
.apu_waddr_i (apu_waddr_ex),

.apu_read_regs_i (apu_read_regs),
.apu_read_regs_valid_i (apu_read_regs_valid),
.apu_read_dep_o (apu_read_dep),
.apu_write_regs_i (apu_write_regs),
.apu_write_regs_valid_i(apu_write_regs_valid),
.apu_write_dep_o (apu_write_dep),
.apu_read_regs_i (apu_read_regs),
.apu_read_regs_valid_i (apu_read_regs_valid),
.apu_read_dep_o (apu_read_dep),
.apu_read_dep_for_jalr_o(apu_read_dep_for_jalr),
.apu_write_regs_i (apu_write_regs),
.apu_write_regs_valid_i (apu_write_regs_valid),
.apu_write_dep_o (apu_write_dep),

.apu_perf_type_o(perf_apu_type),
.apu_perf_cont_o(perf_apu_cont),
Expand Down
60 changes: 31 additions & 29 deletions rtl/cv32e40p_ex_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -94,6 +94,7 @@ module cv32e40p_ex_stage
input logic [2:0][5:0] apu_read_regs_i,
input logic [2:0] apu_read_regs_valid_i,
output logic apu_read_dep_o,
output logic apu_read_dep_for_jalr_o,
input logic [1:0][5:0] apu_write_regs_i,
input logic [1:0] apu_write_regs_valid_i,
output logic apu_write_dep_o,
Expand Down Expand Up @@ -336,13 +337,14 @@ module cv32e40p_ex_stage
.active_o(apu_active),
.stall_o (apu_stall),

.is_decoding_i (is_decoding_i),
.read_regs_i (apu_read_regs_i),
.read_regs_valid_i (apu_read_regs_valid_i),
.read_dep_o (apu_read_dep_o),
.write_regs_i (apu_write_regs_i),
.write_regs_valid_i(apu_write_regs_valid_i),
.write_dep_o (apu_write_dep_o),
.is_decoding_i (is_decoding_i),
.read_regs_i (apu_read_regs_i),
.read_regs_valid_i (apu_read_regs_valid_i),
.read_dep_o (apu_read_dep_o),
.read_dep_for_jalr_o(apu_read_dep_for_jalr_o),
.write_regs_i (apu_write_regs_i),
.write_regs_valid_i (apu_write_regs_valid_i),
.write_dep_o (apu_write_dep_o),

.perf_type_o(apu_perf_type_o),
.perf_cont_o(apu_perf_cont_o),
Expand Down Expand Up @@ -387,28 +389,28 @@ module cv32e40p_ex_stage
assign fpu_fflags_o = apu_rvalid_q ? apu_flags_q : apu_flags_i;
end else begin : gen_no_apu
// default assignements for the case when no FPU/APU is attached.
assign apu_req_o = '0;
assign apu_operands_o[0] = '0;
assign apu_operands_o[1] = '0;
assign apu_operands_o[2] = '0;
assign apu_op_o = '0;
assign apu_req = 1'b0;
assign apu_gnt = 1'b0;
assign apu_result = 32'b0;
assign apu_valid = 1'b0;
assign apu_waddr = 6'b0;
assign apu_stall = 1'b0;
assign apu_active = 1'b0;
assign apu_ready_wb_o = 1'b1;
assign apu_perf_wb_o = 1'b0;
assign apu_perf_cont_o = 1'b0;
assign apu_perf_type_o = 1'b0;
assign apu_singlecycle = 1'b0;
assign apu_multicycle = 1'b0;
assign apu_read_dep_o = 1'b0;
assign apu_write_dep_o = 1'b0;
assign fpu_fflags_we_o = 1'b0;
assign fpu_fflags_o = '0;
assign apu_req_o = '0;
assign apu_operands_o[0] = '0;
assign apu_operands_o[1] = '0;
assign apu_operands_o[2] = '0;
assign apu_op_o = '0;
assign apu_req = 1'b0;
assign apu_gnt = 1'b0;
assign apu_result = 32'b0;
assign apu_valid = 1'b0;
assign apu_waddr = 6'b0;
assign apu_stall = 1'b0;
assign apu_active = 1'b0;
assign apu_ready_wb_o = 1'b1;
assign apu_perf_wb_o = 1'b0;
assign apu_perf_cont_o = 1'b0;
assign apu_perf_type_o = 1'b0;
assign apu_singlecycle = 1'b0;
assign apu_multicycle = 1'b0;
assign apu_read_dep_o = 1'b0;
assign apu_read_dep_for_jalr_o = 1'b0;
assign apu_write_dep_o = 1'b0;
assign fpu_fflags_o = '0;
end
endgenerate

Expand Down
19 changes: 14 additions & 5 deletions rtl/cv32e40p_id_stage.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,7 @@ module cv32e40p_id_stage
output logic [2:0][5:0] apu_read_regs_o,
output logic [2:0] apu_read_regs_valid_o,
input logic apu_read_dep_i,
input logic apu_read_dep_for_jalr_i,
output logic [1:0][5:0] apu_write_regs_o,
output logic [1:0] apu_write_regs_valid_o,
input logic apu_write_dep_i,
Expand Down Expand Up @@ -804,6 +805,12 @@ module cv32e40p_id_stage
// dependency checks
always_comb begin
unique case (alu_op_a_mux_sel)
OP_A_CURRPC: begin
if (ctrl_transfer_target_mux_sel == JT_JALR) begin
apu_read_regs[0] = regfile_addr_ra_id;
apu_read_regs_valid[0] = 1'b1;
end
end // OP_A_CURRPC:
OP_A_REGA_OR_FWD: begin
apu_read_regs[0] = regfile_addr_ra_id;
apu_read_regs_valid[0] = 1'b1;
Expand Down Expand Up @@ -847,7 +854,7 @@ module cv32e40p_id_stage
apu_read_regs_valid[2] = 1'b1;
end
OP_C_REGC_OR_FWD: begin
if (alu_op_a_mux_sel != OP_A_REGC_OR_FWD) begin
if ((alu_op_a_mux_sel != OP_A_REGC_OR_FWD) && (ctrl_transfer_target_mux_sel != JT_JALR)) begin
apu_read_regs[2] = regfile_addr_rc_id;
apu_read_regs_valid[2] = 1'b1;
end else begin
Expand Down Expand Up @@ -1089,7 +1096,8 @@ module cv32e40p_id_stage

cv32e40p_controller #(
.COREV_CLUSTER(COREV_CLUSTER),
.COREV_PULP (COREV_PULP)
.COREV_PULP (COREV_PULP),
.FPU (FPU)
) controller_i (
.clk (clk), // Gated clock
.clk_ungated_i(clk_ungated_i), // Ungated clock
Expand Down Expand Up @@ -1158,9 +1166,10 @@ module cv32e40p_id_stage
.mult_multicycle_i(mult_multicycle_i),

// APU
.apu_en_i (apu_en),
.apu_read_dep_i (apu_read_dep_i),
.apu_write_dep_i(apu_write_dep_i),
.apu_en_i (apu_en),
.apu_read_dep_i (apu_read_dep_i),
.apu_read_dep_for_jalr_i(apu_read_dep_for_jalr_i),
.apu_write_dep_i (apu_write_dep_i),

.apu_stall_o(apu_stall),

Expand Down

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