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Questasim + bare-metal program + physical memory access #779
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Thanks for your elaborate explanation. We found a neat solution that works pretty well. A small adjustment to the rtl code (i.e. correct use of the Since this is probably very useful for anyone developing new SoC or core extensions, should I add a separate PR for that? As far as I can see, there is not really software code in the repo so far, that is why I am asking.. |
I need to be able to do this as well, i.e. develop bare metal software that does physical memory accesses as part of cva6 integration into a SoC device. I thinks this should be added. Rationale: This assists SoC integration teams by:
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Hi @andreaskuster, I think this issue is resolved but it is not certain. Can you provide an update? |
Hi @MikeOpenHWGroup |
Related to #1569 |
I am in currently in the process of integrating a DMA engine into the CVA6 SoC.
I would like to write a simple driver i.e. for the start, just read from / write to device registers in the physical memory space.
(1) Following the
Running User-Space Applications
with the frist-stage bootloader, pk and bbl i.e.make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1
does work, however, we end up in virtual memory. Is there an (easy) way to either directly access physical memory from there or map it into the user space app? (i.e. accessing0x8000_0000
produces a segfault).Even though the
--disable-vm
option is still present, it does not seem to still be active anymore: riscv-software-src/riscv-pk#200(2) Using the uart driver and running this as the main application
make sim elf-bin=main.elf batch-mode=1
did not work.(3) Adding the
fromhost
andtohost
functionality from vm.c omited the warning, however, did not produce any output.Any suggestions or examples on how this can be done efficiently would be appreciated.
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