🔖 Release 0.6.1

openhwgroup · Jul 10, 2019 · 4a241d4 · 4a241d4
2 parents b7ca052 + 029dc52
commit 4a241d4
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diff --git a/docs/CHANGELOG.md b/docs/CHANGELOG.md
@@ -14,6 +14,12 @@ Versions of the IP in the same major relase are "pin-compatible" with each other
 ### Changed
 ### Fixed
 
+
+## [0.6.1] - 2019-07-10
+
+### Fixed
+- A bug where the div/sqrt unit could lose operations in flight
+
 ## [0.6.0] - 2019-07-04
 
 ### Changed

diff --git a/src/fpnew_divsqrt_multi.sv b/src/fpnew_divsqrt_multi.sv
@@ -155,6 +155,7 @@ module fpnew_divsqrt_multi #(
   logic in_ready;               // input handshake with upstream
   logic div_valid, sqrt_valid;  // input signalling with unit
   logic unit_ready, unit_done;  // status signals from unit instance
+  logic op_starting;            // high in the cycle a new operation starts
   logic out_valid, out_ready;   // output handshake with downstream
   logic hold_result;            // whether to put result into hold register
   logic data_is_held;           // data in hold register is valid
@@ -167,8 +168,9 @@ module fpnew_divsqrt_multi #(
   assign inp_pipe_ready[NUM_INP_REGS] = in_ready;
 
   // Valids are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr.
-  assign div_valid  = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i;
-  assign sqrt_valid = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i;
+  assign div_valid   = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i;
+  assign sqrt_valid  = in_valid_q & (op_q != fpnew_pkg::DIV) & in_ready & ~flush_i;
+  assign op_starting = div_valid | sqrt_valid;
 
   // FSM to safely apply and receive data from DIVSQRT unit
   always_comb begin : flag_fsm
@@ -243,9 +245,9 @@ module fpnew_divsqrt_multi #(
   AuxType result_aux_q;
 
   // Fill the registers everytime a valid operation arrives (load FF, active low asynch rst)
-  `FFL(result_is_fp8_q, input_is_fp8,                 in_valid_q, '0)
-  `FFL(result_tag_q,    inp_pipe_tag_q[NUM_INP_REGS], in_valid_q, '0)
-  `FFL(result_aux_q,    inp_pipe_aux_q[NUM_INP_REGS], in_valid_q, '0)
+  `FFL(result_is_fp8_q, input_is_fp8,                 op_starting, '0)
+  `FFL(result_tag_q,    inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0)
+  `FFL(result_aux_q,    inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0)
 
   // -----------------
   // DIVSQRT instance