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Misaligned Faults concurrent with TLB miss #841

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rosethompson opened this issue Jun 19, 2024 · 1 comment
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Misaligned Faults concurrent with TLB miss #841

rosethompson opened this issue Jun 19, 2024 · 1 comment
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Misaligned faults may be asserted when a TLB miss occurs. Because Wally only implements misaligned support for cacheable memory, the address must be translated before cacheablity is known. Table 15 of the privileged spec defines the priority of faults and Wally places misaligned after page faults. of We need to create a test case and update the HPTW to suppress these faults during a TLB miss.
@davidharrishmc davidharrishmc added the bug Something isn't working label Sep 12, 2024
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Resolved with PR #975

davidharrishmc added a commit that referenced this issue Oct 1, 2024
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Merge pull request #975 from rosethompson/main
450191a 
Fixes Issue #841 Misaligned TLB misses
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