Fixes Issue #841 Misaligned TLB misses #975
Open
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
checks cached accesses which should not cause misaligned faults and then uses PBMT to disable cachablity.
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Checks if the TLB misses and if so suppresses load and store misaligned faults. Added non-self checking test to verify behavior. ImperasDV does not match. I believe there may be a different bug either with ImperasDV or our implementation. The test uses PBMT to make a misaligned uncached request with a TLB miss. The TLB correctly suppresses the fault until the TLB is filled. However, ImperasDV says the load should not cause the fault.