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[Makefile] Bump Verilator to v5.012
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mp-17 committed Sep 8, 2023
1 parent bccb9dd commit 5327d45
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Showing 3 changed files with 3 additions and 2 deletions.
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ LLVM_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-llvm
ISA_SIM_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-isa-sim
ISA_SIM_MOD_INSTALL_DIR ?= ${INSTALL_DIR}/riscv-isa-sim-mod
VERIL_INSTALL_DIR ?= ${INSTALL_DIR}/verilator
VERIL_VERSION ?= v4.214
VERIL_VERSION ?= v5.012
DTC_COMMIT ?= b6910bec11614980a21e46fbccc35934b671bd81

CMAKE ?= cmake
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1 change: 1 addition & 0 deletions hardware/Makefile
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Expand Up @@ -179,6 +179,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
-Wno-UNSIGNED \
-Wno-WIDTH \
-Wno-WIDTHCONCAT \
-Wno-ENUMVALUE \
--hierarchical \
tb/verilator/waiver.vlt \
--Mdir $(veril_library) \
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2 changes: 1 addition & 1 deletion toolchain/verilator
Submodule verilator updated 2940 files

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