Improve reliability at higher bus speeds #6050
Merged
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
cea76e5 calculates timings for arbitrary clock speeds, but it does so aiming for a 50% SCL duty cycle. This is the wrong goal, particularly for high clock speeds, but it doesn't allow the device sufficient time to pull the bus low to issue an ACK.
Change the algorithm to aim for the minimum SCL high time (tHIGH) for the requested speed according to the I2C Specification, using linear interpolation between the values for the standard speeds.