Add Sstc extension

[ved-rivos]

No description provided.

[arichardson]

A few minor comments, will aim to do a full review of the logic soon

[github-actions]

Test Results

712 tests  ±0   712 ✅ ±0   0s ⏱️ ±0s
  6 suites ±0     0 💤 ±0 
  1 files   ±0     0 ❌ ±0 

Results for commit e7a5236. ± Comparison against base commit 40ed0c5.

♻️ This comment has been updated with latest results.

[Timmmm]

LGTM, needs rebasing & there are some old style bit accesses (menvcfg.STCE()).

Also do you need to handle the fact that mip[STI] is writable or not depending on whether this extension is implemented:

If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode. If the stimecmp (supervisor-mode timer compare) register is implemented, STIP is read-only in mip and reflects the supervisor-level timer interrupt signal resulting from stimecmp.