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Fixes to Fastino V1.0 #71
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The second shield pin is intentionally floated.
faster signal rise time
* lower R48 to 2k2 * connect IC10 directly to EEM0_I2C (before T6, T9) * connect IC10 and config pins to P3V3_MP
@pathfinder49 use variants to mark components as DNP |
all components have a dedicated layer (M15) which can be used as a clearance indicator |
Are these minium requirements? For capacitors, the markings are much larger than the footprint. |
Ace, thanks @pathfinder49 ! @gkasprow are you okay to do a careful review of the new layout, paying close attention to SI and cross-talk? Once that's done I'd love to get a new batch into production |
@pathfinder49 btw https://help.github.com/en/enterprise/2.16/user/github/managing-your-work-on-github/closing-issues-using-keywords is a really nice feature to ensure the resolved issues get closed automatically when the PR is merged. |
@gkasprow The component clearences inbdicated on M15 tend to be rectangular. This does not match the actual component shpes. For example: the the 16 DAC pins leave the corners of the DAC clearance box physically un-occupied. Are these required to be unoccupieed? |
@gkasprow Hope you're doing well. When you have a chance, could please you take a look at my changes? |
I prefer to do it from my computer. |
Did this get merged? Should we close now? |
I believe @gkasprow didn't merge this, but re-comitted and pushed the final state to master. |
@pathfinder49 my understanding is that all the work in this PR made its way into v1.1 so it's safe to close the PR. Please re-open if that's not the case. |
I've addressed all issues with V1.0 I'm aware of. Specifically I've done addressed issues:
I still need to figure out how to mark the parallel termination capacitors as DNP. I'm also unsure if component clearances may pose a problem (design rules pass).
@gkasprow Could you please review my changes?