Fixes to Fastino V1.0

[pathfinder49]

I've addressed all issues with V1.0 I'm aware of. Specifically I've done addressed issues:

1. Fixed the DAC resistor package routing (discussed in Fastino testing #42)
2. Connected P3V3_MP to the EEM cables P3V3_MP and P3V3MP #47
3. Fixed the circular i2c dependecy and R48 i2c broken with AFE_PWR disabled #48
4. Grounded IC3 housing IC3 (CC10-1212DF-E) housing not grounded #53
5. Increased P/N12V0A capacitance 3-fold (N12V0A oscillating on some boards #54 & IC13 (LT3045EDD#PBF) out of spec #69)
6. Add 62 ohm series termination and change parallel termination to 15 pF, 0603 capacitors (not yet DNP) DAC Digital Trace Termiantion Improvements #63
7. Rerouted digital and analogue DAC traces Re-Route DAC Digital Traces #64
8. Removed CMCs Remove CMCs? #65
9. Reduced polygon-via clearance Reduce ground clearance around vias? #67

I still need to figure out how to mark the parallel termination capacitors as DNP. I'm also unsure if component clearances may pose a problem (design rules pass).

@gkasprow Could you please review my changes?

[gkasprow]

@pathfinder49 use variants to mark components as DNP

[gkasprow]

all components have a dedicated layer (M15) which can be used as a clearance indicator

[pathfinder49]

all components have a dedicated layer (M15) which can be used as a clearance indicator

Are these minium requirements? For capacitors, the markings are much larger than the footprint.

[hartytp]

Ace, thanks @pathfinder49 !

@gkasprow are you okay to do a careful review of the new layout, paying close attention to SI and cross-talk? Once that's done I'd love to get a new batch into production

[hartytp]

@pathfinder49 btw https://help.github.com/en/enterprise/2.16/user/github/managing-your-work-on-github/closing-issues-using-keywords is a really nice feature to ensure the resolved issues get closed automatically when the PR is merged.

[pathfinder49]

all components have a dedicated layer (M15) which can be used as a clearance indicator

@gkasprow The component clearences inbdicated on M15 tend to be rectangular. This does not match the actual component shpes. For example: the the 16 DAC pins leave the corners of the DAC clearance box physically un-occupied. Are these required to be unoccupieed?

[pathfinder49]

@gkasprow Hope you're doing well. When you have a chance, could please you take a look at my changes?

[pathfinder49]

#72 (comment)

I think it is good enough. Every project can be done better, but here the main goal is high channel isolation. Let's produce it;

@gkasprow @cjbe @hartytp Could one of you please merge this?

[gkasprow]

I prefer to do it from my computer.

[hartytp]

Did this get merged? Should we close now?

[pathfinder49]

Did this get merged? Should we close now?

I believe @gkasprow didn't merge this, but re-comitted and pushed the final state to master.

[hartytp]

@pathfinder49 my understanding is that all the work in this PR made its way into v1.1 so it's safe to close the PR. Please re-open if that's not the case.