Skip to content

Kasli

Jump to bottom
Robert Jordens edited this page Jun 8, 2017 · 70 revisions

Overview

Kasli is low-cost FPGA carrier, capable of controlling at least 8 Eurocard extension modules. It can act as either an ARTIQ master, or as a slave connected to the master via DRTIO.

Rendering (above) Mockup image. Image may not reflect latest specification (below).

Specification/initial design

Kasli is compatible with the Sinara EEM standard. Its design is based on the discussion in issue #129.

Front panel connections:

  • 3 SFP connectors for Ethernet (if Kasli is the master) and DRTIO (one upstream, two downstream).
    • SFP1: Ethernet in stand-alone (if Kasli is master), DRTIO upstream otherwise
    • SFP2: DRTIO downstream
    • SFP3: DRTIO downstream or special purpose.
  • Remaining transceivers:
    • SATA1 ("host" pinout, not "disk"/"reversed"): DRTIO downstream or special purpose
  • 1 micro USB for JTAG and serial console.
  • 1 SMA to/from the clock recovery chip, function selectable by jumpers and/or on-board mux:
    • RTIO reference clock input in master/stand-alone mode (10 dBm sine/square)
    • recovered DRTIO clock output in slave mode (10 dBm square)
  • 1 SMA:
    • DDS/PLL clock input that is sent to a clock fan-out.

EEM connectivity depending on pin count:

  • If only 8 EEMs can be supported:
    • EXT0-3: backplane+IDC
    • EXT4-7: IDC
  • If more than eight EEMs can be supported:
    • EXT0-3: IDC
    • EXT4-7: IDC
    • EXT8-...: backplane

Rear connections:

  • Barrel connector for +12V power, used for Kasli and passed through to the EEM IDCs. 12V power should be dimensioned to the EEMs (0.5 A for a single Zotino and Kasli should not be a bottle neck). Preferrably a locking barrel connector.
  • DIN 41612 96 position connector to backplane.
  • DIN 41612/Barrel mechanical conlficts to be resolved.

Rack-internal connections:

  • Hosts 8 EEMs using standard EEM headers
  • Up to 4 EEMs via backplane (+ clocks). Either as an alternative connectivity to the first four EEM IDC connectors, or as an additional four EEMs (numbers 8-12)
  • 1 SATA (wired as master/host) connected to a transciever
  • Several SMA (or smaller) connectors from the clock fan-out if there is space. Single-ended.

General:

  • FPGA: 7 Series Artix, a handful of transcievers, big enough to run a CPU, DRAM controller and a bunch of ARTIQ RTIO PHYs, maybe a 50T in FGG484
  • Some DDR3, 64-bit wide, SPI flash, a few (2-4) LEDs, USB FTDI JTAG + UART
  • Same clocking/clock recovery/jitter cleaning as Sinara Metlino (SI5324 + oscillator + bootstrap oscillator)

Mechanical:

  • Kasli should be 4HP wide.
  • Two mechanical use-cases:
    • Kasli and a bunch of EEMs in a 3Ux19" Sub-Rack. Power supply in the back.
    • Kasli and a one (or a few) EEMs in some small enclosure. Distributed over the lab, small external wall-wart power supply.

Screening:

  • TBD

Thermal:

  • Should be able to operate without forced air or an on-board fan, i.e. rack convection should be sufficient.
Clone this wiki locally