Minutes20160914

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1. Wednesday Sept 7

start at 0900 at WUT

Activity 1 (2 hr) :: project management planning
lead: Jordens/Britton

• develop weekly plan for design-layout phase (4-weeks + 6-weeks)
• develop list of tasks and studies
• assign priority, difficulty, order of implementation
• plan structure of weekly reports and teleconferences
• discuss m-labs project leadership
• how to handle design changes, regressions (formal check off?, cost/time deltas?)

Activity 2 (2 hr) :: m-labs advice on hardware design
lead: Jordens
Design choices that m-labs is concerned about relating to Sayma design (8/25).

• DRAM choice
• multi-board-multi-chip-sync (clock distribution chip meeting JESD204B subclass1 specification)
• FPGA {family, size, speed grade}
• Ethernet MAC inclusion (or not)
• choice of serial interface chip
• thermal stability required for DAC stability at the LSB level
• management, maintenance, review and integration of WUT housekeeping code
• WUT subcontracting with m-labs to write test benches for hardware
• configuration of on-board peripherals like power, PLL< clock distribution IC’s; m-labs (FPGA) or WUT (uP)?

LUNCH

Activity 3 (2.5 hr) :: discussion with Oxford
lead: Tom Harty, Weida Zhang, Britton/Jordens

• Britton/Jordens: review Warsaw discussion from Tuesday relating to det-lac mcs
• Zhang: power supply noise minimization/rejection (source document “Milldown Board Phase Noise Measurement Report 20151102 (2).docx”)
• Harty/Zhang: DAC_CLK generation by daughter card (source document “Oxford time distribution 20160618.pdf”)
• Harty/Zhang: analog input daughter card (Aug 2 email thread)

Activity 3 (1 hr) :: discussion of other components
lead: Britton/Jordens
other ICs on devices:

• m-labs asks confirm that “IPMI, PS config, system management, FTDI config, JESD204B (but not synchronization) are covered by WUT.”
  metlino_motherboard
• discuss inclusion of hard-core ARM IC (future-proofing, ETH)
• XCO choice
  sayma_motherboard
• precision voltage reference needs specification
• XCO choice
  sayma_daughter_output_logiq_2w_0
• analog component temperature coefficients: DACs, amplifiers, etc.
• power supply noise rejection

Activity 4 (1 hr) :: funding mechanisms/grants beyond present project scope

• Kasprowicz: EU Horizon 2020
• Britton: OSD
• European partners academic, commercial
• discuss priorities for respective partners

Activity 4 (0.5 hr) :: hardware distribution plan
lead: Kasprowicz

• how has this worked in the past?
• work with commercial partner like Creotech to collect orders, build, test and distribute boards
• markup for on-going board support and bug fixes?
• cost sharing structure?

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1. Thursday Sept 8
   Jordens departs by train at 1000
   Britton departs by plane at 1245