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Kasli

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hartytp edited this page Feb 21, 2017 · 70 revisions

Overview

Kasli is low-cost FPGA carrier, capable of controlling 8 [Eurocard extension modules](Eurocard extension boards). It can act as either an ARTIQ master, or as a slave connected to the master via DRTIO.

Mockup: obraz

Specification/initial design

Kasli is compatible with the Sinara [EEM standard](Eurocard Extension Modules). It's design is based on the discussion in issue #129.

Front panel connections:

  • 3 SPF connectors for DRTIO
  • 1 micro USB for JTAG
  • 1 SMA, used for: RTIO reference clock input in master/stand-alone mode; recovered DRTIO clock output in slave mode. Inputs are +10dBm, 50Ohm single-end sine or square-wave, outputs are ?.
  • 1 SMA, used for either (selectable by jumpers and on-board mux): copy of first SMA (for daisy-chaining); or a second clock input that is sent to the backplane (if we decide to use one).

Internal connections:

  • Hosts 8 EEMs using standard EEM headers
  • 4 EEMs via backplane (+ clocks) ??
  • 1 SATA connected to a transciever

General:

  • Artix, a handful of transcievers, big enough to run a CPU, DRAM controller and a bunch of ARTIQ RTIO PHYs, maybe a 50T in FGG484
  • DDR3, SPI flash, a few LEDs, USB FTDI JTAG + UART
  • Same clocking/clock recovery/jitter cleaning as Sinara Metlino (SI5324 + oscillator + bootstrap oscillator)
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