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Metlino

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hartytp edited this page Mar 4, 2017 · 11 revisions

Metlino uTCA MCH

Metlino is a uTCA MCH (rack master) optimised for use in Sinara. It can be operated as either an ARTIQ master or slave, connected to the master via DRTIO.

Metlino occupies MCH tongues (to do: explain what a tongue is somewhere) 3 & 4. To operate, it requires Mordovia to fill tongue 2 and NAT-MCH-Base12-GbE to fill tongue 1. All three boards mount on a shared front-panel.

To do: comment on how this fits in with the RTMs, and what happens with all the clocks. Diagram?

Metlino provides 64 LVDS IOs, accessible through 2 VHDCI connectors, as well as ? FMCs. The VHDCIs are compatible with the VHDCI carrier and Eurocard extension modules.

The design files are located in ARTIQ_EE/PCB_Metlino, the schematic is here.

Specification

  • FPGA is Kintex UltraScale KU040 speed grade -1 (p/n XCKU040-1FFVA1156C)
  • Connectors
  • RAM
  • Etc
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