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Look at supporting tftp booting using a "high port" which can be opened by non-root users #6

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mithro opened this issue Jan 16, 2018 · 11 comments
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Look at supporting tftp booting using a "high port" which can be opened by non-root users #6

mithro opened this issue Jan 16, 2018 · 11 comments

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@mithro
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mithro commented Jan 16, 2018 •
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"Low" ports can only be opened by root (or user with special privileges) -- https://www.staldal.nu/tech/2007/10/31/why-can-only-root-listen-to-ports-below-1024/

tftp by default uses port 68 (https://en.wikipedia.org/wiki/Trivial_File_Transfer_Protocol) -- which is a low port.

This means tftp server has to be run as root, which kind of sucks.

Instead it would be good if the tftp server ran on an alternative port that a user can bind too.
@mithro
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mithro commented Jan 16, 2018 •
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https://github.com/enjoy-digital/litex/blob/master/litex/soc/software/libnet/tftp.c#L7

GitHub
litex - Build your hardware, easily!

@mithro
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mithro commented Jan 16, 2018

Python Libraries -

@ewenmcneill
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atftpd will take a -p PORT option to force it to listen on a different port; in.tftpd seems to have a -R PORT:PORT option to constrain the server port to be in that range which may be sufficient (seems to support multiple ports to allow simultaneous transfer from the same client).

litex/soc/software/net/tftp.c is trivially modified to take server_port as a parameter, which allows litex/soc/software/bios/boot.c to specify the TFTP port in a similar manner to the IP. (The callback just replies to the port it received traffic from which is simple, if not very secure.)

Once server_port is under BIOS control it should be relatively simple to have it try a list of ports in turn, at least for the first file, until it finds one that works.

@mithro
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mithro commented Jan 18, 2018

@ewen-naos-nz - SGTM!

@ewenmcneill
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@mithro: litex pull request 52 - BIOS: Support alternative TFTP server port.

When compiled with TFTP_SERVER_PORT=6969 exported in the environment, it will try both UDP/6969 and then UDP/69 (for boot.bin) during boot. Eg,

(LX P=arty C=or1k.linux F=linux) ewen@parthenon:/src/fpga-miniconf/litex-buildenv$ make firmware-connect
flterm --port=/dev/ttyUSB1 --speed=115200
[FLTERM] Starting...

LiteX SoC BIOS (or1k)
(c) Copyright 2012-2018 Enjoy-Digital
(c) Copyright 2007-2018 M-Labs Limited
Built Jan 18 2018 13:11:19

BIOS CRC passed (189f291e)
Initializing SDRAM...
Memtest OK
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
Booting from network...
Local IP : 192.168.100.50
Remote IP: 192.168.100.100
Fetching from: UDP/6969
Jan 18 13:23:40 parthenon atftpd[10761.139727563720448]: socket may listen on any address, including broadcast
Jan 18 13:23:40 parthenon atftpd[10761.139727563720448]: Serving boot.bin to 192.168.100.50:7642
Unable to download boot.bin over TFTP
Fetching from: UDP/69
[....]
Successfully downloaded 3730908 bytes from boot.bin over TFTP

We still need to, eg, support starting TFTP server on alternative port.

@ewenmcneill
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FTR: once enjoy-digital/litex merges pull request, we'll also have to update our git submodule to point at a newer version... and upstream already includes a few other changes AFAICT.

Ewen

@mithro
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mithro commented Jan 18, 2018

@ewen-naos-nz Merged the enjoy-digital/litex pull request -- enjoy-digital/litex#52

@ewenmcneill
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@mithro timvideos/litex-buildenv#10 for our side of the change. At least with atftpd this allows running without root.

It might still be worth providing, eg, Python-based TFTP server to reduce need to install system dependencies that auto-start daemons. (But I suspect some users will be forced to interact with their firewall config anyway.)

@ewenmcneill
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Of note, the "built in" qemu TFTP server (used in scripts/build-qemu.sh in the user network config) currently only runs on UDP/69, so is relying on BIOS fallback to trying UDP/69. If someone can figure out a way to tell it to listen on a different port, it should now have TFTP_SERVER_PORT in its environment to know which port is intended.

@mithro
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mithro commented Jan 18, 2018

This has been mostly done thanks to @ewen-naos-nz -- I'll create a seperate issue for the Python-based TFTP server.

@mithro mithro closed this as completed Jan 18, 2018
@ewenmcneill
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ewenmcneill commented Jan 18, 2018 •
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tftpy code appears to be at https://github.com/msoulier/tftpy now. Last update 2017 (cf sf.net page last updated around 2010). Seems to have a listenport option on the TFTPServer class, so at least could be given a simple frontend to listen on a different port.

py3tftp (https://github.com/sirMackk/py3tftp) is server only, takes port on command line, and defaults to UDP/9069.

Potentially either one would do as a "simple TFTP Server run as user".

GitHub
tftpy - Pure Python TFTP library
GitHub
py3tftp - An asynchronous TFTP server in pure Python 3.5

@ewenmcneill ewenmcneill mentioned this issue Jan 18, 2018
Open
mithro added a commit that referenced this issue Jan 26, 2018
@mithro
Updating submodules.
314f9e6 
 * flash_proxies changed from 070d8b2 to c506426
    * c506426 - Merge pull request #3 from cr1901/master <Robert Jördens>
    * bf63a40 - Add Spartan 7 (xc7s50) bitstream, plus corresponding logic to regenerate. <William D. Jones>

 * litedram changed from a09b7a0 to 13d41f6
    * 13d41f6 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell>
    * 72b1b10 - Fix all remaining indentation issues in python code <Felix Held>

 * litepcie changed from 09dbd6d to 945963d
    * 945963d - phy/s7pciephy: set sys_rst_n to 1 if no rst_n pad <Florent Kermarrec>
    *   5590f11 - Merge pull request #7 from felixheld/indentation-fixes <Tim Ansell>
    |\
    | * d602010 - Fix all remaining indentation issues in python code <Felix Held>
    * 9469929 - Merge pull request #6 from felixheld/indentation-fixes <Tim Ansell>
    * 5376257 - fix code indentation <Felix Held>

 * litesata changed from a8bf0d4 to af00fa6
    * af00fa6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell>
    * 220b601 - Fix all indentation issues in python code <Felix Held>

 * litescope changed from 7757727 to aa44da3
    * aa44da3 - example_designs/make.py: fix typos <Florent Kermarrec>
    * 72e71e7 - core: simplify <Florent Kermarrec>
    * 7803591 - Merge pull request #9 from felixheld/indentation-fixes <Tim Ansell>
    * febb358 - Fix all remaining indentation issues in python code <Felix Held>

 * liteusb changed from 9a78586 to 0b05b6c
    * 0b05b6c - +x on scripts <Florent Kermarrec>

 * litevideo changed from c9770cc to 8d940dc
    * 8d940dc - output: add raw support (10 bits tmds in dram), untested <Florent Kermarrec>
    * 5c168aa - input: add capability to get raw 10 bits data when not using dram port <Florent Kermarrec>
    * dcd9624 - input/edid: simplify scl inversion <Florent Kermarrec>
    *   3b04d1b - Merge pull request #14 from bunnie/scl-merge <enjoy-digital>
    |\
    | * 7845c85 - add inverted attribute to SCL <bunnie>
    |/
    *   a7fd5f6 - Merge pull request #13 from felixheld/indentation-fixes <Tim Ansell>
    |\
    | * 34b1a0f - Fix all remaining indentation issues in python code <Felix Held>
    |/
    * 4d6bc46 - input/datacapture: simplify inverted data in S7DataCapture <Florent Kermarrec>
    * af096a5 - input/clocking/s7: use bufr and fix input connection to mmcm <Florent Kermarrec>
    * 9ebdd1b - output: use new inverted property of pads to invert polarity <Florent Kermarrec>
    * 218b708 - output: add assertion if inverted property is used (since not yet implemented) <Florent Kermarrec>
    * 113bdb7 - input: use new inverted property of pads to invert polarity <Florent Kermarrec>
    * 091c9ec - litevideo: add __init__.py, fix install <Florent Kermarrec>
    * 9aae319 - input: add clk_polarity parameter, rename data_polarities to datas_polarity <Florent Kermarrec>

 * litex changed from v0.1-251-gead88ed6 to v0.1-270-g4f272580
    * 4f272580 - software/common: revert PYTHON to python3 (since breaking things) <Florent Kermarrec>
    * 4e168221 - bios: fix riscv processor print <Florent Kermarrec>
    * d4488748 - sim: rename top module to dut and use --top-module parameter (needed for picorv32 simulation) <Florent Kermarrec>
    *   a3851437 - Merge pull request #59 from q3k/for-upstream/multiple-synthesis-directives <enjoy-digital>
    |\
    | * 21bd26dc - Allow for multiple synthesis directives in specials. <Sergiusz Bazanski>
    |/
    * 67f8718b - minor cleanup <Florent Kermarrec>
    *   d07ddd11 - Merge pull request #58 from q3k/for-upstream/picorv32-support <enjoy-digital>
    |\
    | * 6daf3eab - Implement IRQ software support for RISC-V. <Sergiusz Bazanski>
    | * 2108c97b - Import PicoRV32-specific instruction macros. <Sergiusz Bazanski>
    | * cf74c781 - Write init files that respect CPU's endianness. <Sergiusz Bazanski>
    | * 71764922 - Set the MABI and MArch of the riscv target. <Sergiusz Bazanski>
    | * 7ea5a267 - Enable hardware multiplier and divider in PicoRV32 <Sergiusz Bazanski>
    | * 75e230aa - Replace __riscv__ macros with __riscv. <Sergiusz Bazanski>
    | * 20ed2344 - Export trap signal from PicoRV32. <Sergiusz Bazanski>
    | * b0be5630 - Bump PicoRV32 version. <Sergiusz Bazanski>
    |/
    * 3a5f93db - software/bios: add litex logo <Florent Kermarrec>
    *   d6877300 - Merge pull request #56 from cr1901/mimasv2 <enjoy-digital>
    |\
    | * c553fe2b - Add mimasv2 platform (pulled from litex-buildenv). <William D. Jones>
    |/
    * d6f2f637 - Merge pull request #53 from mithro/allow-forcing-colorama <Tim Ansell>

Full submodule status
--
 f56f329ed23a25d002352dedba1e8f092a47286f edid-decode (heads/master)
 c5064269868396b2c7a78bff28f8e3cf421d1f6e flash_proxies (remotes/origin/HEAD)
 13d41f67ab3070f6af955aa8752c616d034f82f6 litedram (remotes/origin/HEAD)
 8fc716103670e703c7fe98c9bdf653b9b53ca12a liteeth (remotes/origin/HEAD)
 945963d186b3c0287426ef6655e00ad4e250d279 litepcie (remotes/origin/HEAD)
 af00fa613f1b6921e14788dd0ebf301e51009e74 litesata (remotes/origin/HEAD)
 aa44da35c6a232a9e39c43987a3afc9b025ab614 litescope (remotes/origin/HEAD)
 0b05b6c8f9279bb7e476b2c8ae4f39ea88534f08 liteusb (remotes/origin/HEAD)
 8d940dcaf21cffb18cd157e079ec94946878a5d7 litevideo (remotes/origin/HEAD)
 4f2725809e0b9b6cee94cb569c1878f48ab52a15 litex (v0.1-270-g4f272580)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Oct 9, 2019
@mateusz-holenko
Updating submodules.
c357b60 
 * edid-decode changed from 42f5fa4 to 7d26052
    * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil>
    * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao>
    * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil>
    * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil>
    * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil>
    * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil>
    * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil>

 * flash_proxies changed from 1c21ee4 to 01d8f81
    * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq>

 * litedram changed from 6c53996 to 5d1a984
    * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec>
    * d647abd - gen: fix with_wishbone <Florent Kermarrec>
    * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec>
    * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec>
    * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec>
    * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec>
    * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt>
    * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt>
    * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec>
    * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec>
    * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec>
    * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec>
    * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec>
    * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec>
    * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec>
    * 40b4c62 - test/test_init: fix <Florent Kermarrec>
    * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec>
    * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec>
    * 6e176d4 - init: split by memtype <Florent Kermarrec>
    * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec>
    * bf5883c - rename sdram_init to init <Florent Kermarrec>
    * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec>
    * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec>
    * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec>
    * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec>
    * 00ecb87 - gen: add separators <Florent Kermarrec>
    * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec>
    * f678efa - travis: add pyyaml <Florent Kermarrec>
    *   8861d80 - Merge pull request timvideos#91 from sd-fritze/master <enjoy-digital>
    |\
    | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf>
    |/
    * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec>
    * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec>
    * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec>
    * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec>
    * 602ff8b - examples: switch to YAML config files <Florent Kermarrec>
    * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec>
    * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec>
    * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec>
    * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec>
    * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec>
    * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec>
    * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec>
    * f0592ff - core/refresher: add comments <Florent Kermarrec>
    * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec>
    * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec>

 * liteeth changed from ad187d3 to 4d9e74f
    * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec>
    * 4bc79ce - examples/targets/core: update <Florent Kermarrec>
    * cd0eaa9 - Merge pull request timvideos#19 from jersey99/master <enjoy-digital>
    * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla>

 * litepcie changed from 71c9a3a to 47e76f4
    * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec>
    * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec>
    * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec>
    * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec>

 * litescope changed from 9e3b9d8 to 7a9fa9d
    * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec>
    * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec>
    * 69a8df0 - Merge pull request timvideos#14 from DurandA/master <enjoy-digital>
    * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand>

 * litevideo changed from 98e145f to 49bafa4
    * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec>

 * litex changed from e637aa65 to b627a8fe
    * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec>
    *   cc245fc8 - Merge pull request timvideos#275 from pcotret/patch-1 <enjoy-digital>
    |\
    | * e923a88d - Update README (related to issue timvideos#273) <Pascal Cotret>
    * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec>
    * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec>
    * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec>
    * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec>
    * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec>
    |/
    *   e8b90e80 - Merge pull request timvideos#274 from gsomlo/gls-shadow-base <enjoy-digital>
    |\
    | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo>
    |/
    * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec>
    * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec>
    * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec>
    * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec>
    *   2dfe7441 - Merge pull request timvideos#271 from gsomlo/gls-yosys-nowidelut <enjoy-digital>
    |\
    | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo>
    * |   c954ff0c - Merge pull request timvideos#272 from sergachev/fix-comments <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 2f7bd971 - fix comments <Ilia Sergachev>
    * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec>
    |/
    *   960b25a5 - Merge pull request timvideos#270 from gsomlo/gls-csr-upper <enjoy-digital>
    |\
    | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo>
    * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec>
    * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec>
    * |   4bb2827e - Merge pull request timvideos#269 from antmicro/rework_icap <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski>
    * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec>
    * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec>
    * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec>
    * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec>
    * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec>
    * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec>
    * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec>
    * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec>
    * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec>
    * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec>
    * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec>
    * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec>
    * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec>
    * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec>
    * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec>
    * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec>
    * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec>
    * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec>
    * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec>
    * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec>
    * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec>
    * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec>
    * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec>
    * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec>
    * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec>
    * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec>
    * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec>
    * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec>
    * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec>
    * | a4069fc8 - add SERV submodule <Florent Kermarrec>
    * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec>
    * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec>
    * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec>
    * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec>
    * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec>
    * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec>
    * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec>
    * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec>
    * |   836d5b88 - Merge pull request timvideos#266 from xobs/add-moduledoc-autodoc <enjoy-digital>
    |\ \
    | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross>
    | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross>
    * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec>
    * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt>
    * | |   742da31b - Merge pull request timvideos#264 from antmicro/mor1kx_linux <enjoy-digital>
    |\ \ \
    | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski>
    | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski>
    * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec>
    * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec>
    |/ / /
    * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec>
    * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec>
    * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec>
    * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec>
    * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt>
    * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt>
    * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt>
    |/ /
    * |   8b7d8217 - Merge pull request timvideos#263 from xobs/spi-flash-csrfield <enjoy-digital>
    |\ \
    | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross>
    |/ /
    * |   4f659ba4 - Merge pull request timvideos#262 from jersey99/master <enjoy-digital>
    |\ \
    | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla>
    |/ /
    * |   430fee4d - Merge pull request timvideos#261 from xobs/event-documentation <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross>
    |/
    * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec>
    * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec>
    * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec>
    * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec>
    * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec>
    *   f1139c36 - Merge pull request timvideos#259 from xobs/document-timer <enjoy-digital>
    |\
    | * cb7d941a - timer: add documentation <Sean Cross>
    |/
    * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec>
    * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec>
    *   3dc8d294 - Merge pull request timvideos#257 from enjoy-digital/csr_fields <enjoy-digital>
    |\
    | * 9bda614a - csr: update copyrights <Florent Kermarrec>
    | * 29134cc6 - csr: more documentation <Florent Kermarrec>
    | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec>
    | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec>
    | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec>
    | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec>
    | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec>
    | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec>
    | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec>
    |/
    * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec>
    * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec>
    * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec>
    * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec>
    *   cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   a7b5c185 - Merge pull request timvideos#255 from sergachev/fix-crc32 <enjoy-digital>
    | |\
    | | * 2400f0f4 - fix crc32 <Ilia Sergachev>
    | |/
    * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec>
    |/
    * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec>
    * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec>
    * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec>
    * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec>
    * 2638393b - soc_zynq: fix indent <Florent Kermarrec>
    * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec>
    * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec>
    *   6f150a56 - Merge pull request timvideos#254 from mithro/crc-smaller <enjoy-digital>
    |\
    | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell>
    | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell>
    | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross>
    | * a59d0efc - libbase: crc32: add smaller version <Sean Cross>
    * |   27c334d4 - Merge pull request timvideos#252 from mithro/only-change-on-contents <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell>
    |/
    * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec>
    *   19d3acfc - Merge pull request timvideos#251 from micro-FPGA/master <enjoy-digital>
    |\
    | * fb00ee85 - Create atlantic.py <Antti Lukats>
    | *   92e5b4b2 - Merge pull request #2 from enjoy-digital/master <Antti Lukats>
    | |\
    | * | f47e4978 - libero enable enhanced constraints <Antti Lukats>
    * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec>
    * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec>
    * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec>
    * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec>
    * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec>
    * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec>
    * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec>
    * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec>
    * | |   d79cd87d - Merge pull request timvideos#246 from gsomlo/gls-native-rv64 <enjoy-digital>
    |\ \ \
    | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo>
    |/ / /
    * | |   d36f1fb7 - Merge pull request timvideos#244 from atommann/master <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a45dbee5 - changing http to https <atommann>
    | * | 1d957d7a - Update .gitmodules <atommann>
    * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec>
    * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats>
    | |/
    |/|
    * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec>
    * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec>
    * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec>
    * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec>
    * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec>
    * |   f6638ded - Merge pull request timvideos#243 from sergachev/master <enjoy-digital>
    |\ \
    | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev>
    * | |   ccc2cbd9 - Merge pull request timvideos#241 from railnova/zynq <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset>
    |/ /
    * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec>
    * |   383c05e2 - Merge pull request timvideos#240 from danielkucera/patch-1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera>
    |/
    *   2b815f70 - Merge pull request timvideos#235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital>
    |\
    | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo>
    |/
    * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec>
    * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec>
    * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec>
    * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec>
    * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec>
    * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec>
    * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec>
    * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec>
    * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec>
    * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec>
    * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec>
    * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec>
    * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec>
    * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec>
    * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec>
    * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec>
    * 236070fd - cores: -x on spi.py <Florent Kermarrec>
    * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec>
    * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec>
    * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec>
    * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec>
    * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec>
    * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec>
    * ae00482d - Merge pull request timvideos#223 from sergachev/master <enjoy-digital>
    * fdb119cb - support vivado incremental implementation <Ilia Sergachev>

 * litex-renode changed from a57aa47 to b3fdb9b
    *   b3fdb9b - Merge pull request timvideos#13 from antmicro/xip_flash <Tim Ansell>
    |\
    | * 2080118 - Generate LiteX SPI Flash with underlying memory <Mateusz Holenko>
    |/
    * e4ebebf - generate-renode-scripts: be sure kind/variant are in uppercase <Florent Kermarrec>
    * 4c072c8 - litex directory: add missing __init__.py <Florent Kermarrec>
    * dcd3fd8 - Extract HDMI2USB mocserver code to a separate file <Mateusz Holenko>
    * 2bb663f - Extract LiteX configuration parser <Mateusz Holenko>
    * e3c51a4 - Make this repo a proper python package <Mateusz Holenko>
    *   30d044e - Merge pull request timvideos#11 from CarlFK/master <Mateusz Hołenko>
    |\
    | * e2f6a00 - adds --json-file and code to create a json file for the moc server. <Carl Karsten>
    | * b581fd6 - make a main() and parse_args() <Carl Karsten>
    * |   eaeae9b - Merge pull request timvideos#12 from antmicro/rename_litex_spi_flash <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 401babc - Adapt to LiteX_SPI model rename <Mateusz Holenko>
    |/
    *   301b0fd - Merge pull request timvideos#10 from antmicro/fix_gdb <Tim Ansell>
    |\
    | * 8a3a55b - Adapt to GDB API changes in Renode <Mateusz Holenko>
    * 3a4943c - Merge pull request timvideos#9 from antmicro/6-improve_readme <Tim Ansell>
    * cccefd4 - [timvideos#6] Improve the README. <Mateusz Holenko>

 * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd
    * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq>
    * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq>
    * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq>
    * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq>
    * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq>
    * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq>
    * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq>
    * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq>
    * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq>
    * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq>
    * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq>
    * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq>
    * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz>
    * f4fcd10 - fix previous commit <Sebastien Bourdeauducq>
    * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq>

Full submodule status
--
 7d26052f7245664df96079845601ced5335fb2d7 edid-decode (remotes/origin/HEAD)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD)
 5d1a9847aa805034e58eabf376e2807bfed7b133 litedram (remotes/origin/HEAD)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD)
 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD)
 b627a8fe71b55f1987a9cd5181da14cddd3203c1 litex (remotes/origin/HEAD)
 b3fdb9b litex-renode (remotes/origin/HEAD)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this issue Oct 21, 2019
@mateusz-holenko
[timvideos#6] Improve the README.
cccefd4
mateusz-holenko pushed a commit to antmicro/litex-buildenv that referenced this issue Oct 21, 2019
@mithro
Merge pull request timvideos#9 from antmicro/6-improve_readme
3a4943c 
[timvideos#6] Improve the README.
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