WIP: Numato Elbert V2 support #12

mithro · 2018-01-18T07:38:50Z

No description provided.

First attempt; hand translated from Numato UCF file; currently untested.

Copied from targets/mimasv2, with random guesses as to what should be removed from mimasv2 code. In particular: - Mimas v2 supports 100 MHz + 12 MHz clock; Elbert v2 has only 12 MHz clock - Mimas v2 has external SDRAM; Elbert v2 has no external SDRAM - Mimas v2 has physical programming/communications switch over shared USB link - Elbert V2 has only programing over built in USB link; needs separate USBUART module to provide communications **COMPLETELY UNTESTED** at this stage, have not even tried parsing Python...

ewenmcneill · 2018-01-18T08:26:48Z

Current status:`

elbertconfig.py appears to work to program Numato demo
targets/elbertv2.py is a plausible hand translation of Numato UCF file, but not tested
platforms/elbertv2 is cargo cult hacked version of targets/mimasv2 which probably will not work, and likely will not even parse, but is maybe 50% accurate

At this stage would probably benefit from someone with more experience with MiGen/MiSoC/litex looking at definition and figuring out how sane it is, before trying to test with actual hardware. In particular it appears every other supported platform so far as external SDRAM, and Elbert v2 does not have external SDRAM (AFAIK) so it's not clear to me how directly any of the other platform definitions translate.

Branch pushed to GitHub at this stage as backup/to facilitate someone else looking at definitions.

On systems without external SDRAM (eg, Numato Elbert v2), there is no MAIN_RAM_BASE, and we cannot hold a frame buffer as we have only small amounts of in-FPGA SRAM. This should be cleaned up to avoid even compiling the framebuffer / pattern when there is no main ram / MAIN_RAM_BASE, but for now we have stubbed out everything referring to main ram or L2 cache (since the L2 cache is over the external SDRAM). In theory this should still work on systems with MAIN RAM, but currently untested.

UGLY! Hand hacked linker.ld to allow linking on platform without main_ram. TODO: figure out way to generate this conditional on whether there is main ram or not. On platforms with main ram, we tell linker to assume that most things will be in main_ram by the time we execute the code (and the boot loader copies into the main ram). On a platform without main ram, we have to execute directly from the SPI flash (which is mapped in a different location), and need to: (a) ensure that the .text (code) and .rodata (const data) is in the spi flash; and (b) .data (updatable data) and .bss (stack) are in sram (static ram, on FPGA cells)

Commented out cas submodule, as it wasn't being found for elbertv2 (perhaps due to changes needed in third_party/litex?); commented out asserts on frequency copied from mimasv2 as it is unclear what they should be on 12MHz clock (mimasv2 ones are based around 100Mhz clock) At this point, with hand hacked linker.ld, we can compile and link firmware ("make firmware"); but firmware is completely untested.

ewenmcneill · 2018-01-19T02:29:30Z

With a few ugly hacks, just pushed, make firmware will produce a firmware.elf, etc, file -- the litex flashboot() function needed a dependency on main ram worked around (run in place, don't memcpy()), and HDMI / framebuffer / pattern needed stubbing out in order to avoid depending main ram (ideally these wouldn't even be built without main ram support available, as without main ram support there's not enough RAM for a framebuffer anwyay!).

Currently linker.ld assumes that most things will be relocated into main ram, which obviously is not possible on Elbert. As a temporary work around there's a hand hacked linker.ld which has some approximation of relocations for run-in-place from SPI flash. make firmware now completes, and the addresses used seem vaguely plausible, but it's both untested, and probably not 100% correct yet.

We will need a better way to generate/use a linker.ld file with/without main ram to handle this case.

ewenmcneill · 2018-01-19T02:32:36Z

make gateware currently fails, in ISE, due to design errors around the clocks. That section is largely "as copied from Mimas v2" without editing properly, as I am unclear what should be in the PLL / clocks section. Gateware failures below for reference.

Annotating constraints to design from ucf file "top.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:137 - Constraint
[top.ucf(21)]: No appropriate instances for the TNM constraint are driven by
"clk12".

WARNING:ConstraintSystem:56 - Constraint [top.ucf(22)]: Unable to find an active 'TNM' or
'TimeGrp' constraint named 'PRDclk12'.

WARNING:ConstraintSystem:191 - The TNM 'PRDclk12', does not directly or
indirectly drive any flip-flops, latches and/or RAMS and cannot be actively
used by the referencing Period constraint 'TSclk12'. If clock manager blocks
are directly or indirectly driven, a new TNM constraint will not be derived
even though the referencing constraint is a PERIOD constraint unless an
output of the clock manager drives flip-flops, latches or RAMs. This TNM is
used in the following user PERIOD specification:
[top.ucf(22)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
the referenced TNM constraint was removed:
[top.ucf(22)]

Done...

Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive 'FDPE_5' has unconnected output pin
WARNING:NgdBuild:486 - Attribute "DIVIDE" is not allowed on symbol "BUFIO2" of
type "BUFIO2". This attribute will be ignored.
ERROR:NgdBuild:604 - logical block 'BUFIO2' with type 'BUFIO2' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
case mismatch between the block name and the edif or ngc file name, or the
misspelling of a type name. Symbol 'BUFIO2' is not supported in target
'spartan3a'.
WARNING:NgdBuild:486 - Attribute "STARTUP_WAIT" is not allowed on symbol
"crg_periph_dcm_clkgen" of type "DCM_CLKGEN". This attribute will be
ignored.
WARNING:NgdBuild:486 - Attribute "CLKFX_DIVIDE" is not allowed on symbol
"crg_periph_dcm_clkgen" of type "DCM_CLKGEN". This attribute will be
ignored.
WARNING:NgdBuild:486 - Attribute "CLKFX_MULTIPLY" is not allowed on symbol
"crg_periph_dcm_clkgen" of type "DCM_CLKGEN". This attribute will be
ignored.
WARNING:NgdBuild:486 - Attribute "CLKIN_PERIOD" is not allowed on symbol
"crg_periph_dcm_clkgen" of type "DCM_CLKGEN". This attribute will be
ignored.
ERROR:NgdBuild:604 - logical block 'crg_periph_dcm_clkgen' with type
'DCM_CLKGEN' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'DCM_CLKGEN' is
not supported in target 'spartan3a'.
WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
"crg_pll_adv" of type "PLL_ADV". This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "SIM_DEVICE" is not allowed on symbol
"crg_pll_adv" of type "PLL_ADV". This attribute will be ignored.
ERROR:NgdBuild:604 - logical block 'crg_pll_adv' with type 'PLL_ADV' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, case mismatch between the block name and the edif or ngc file name, or
the misspelling of a type name. Symbol 'PLL_ADV' is not supported in target
'spartan3a'.

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 3
Number of warnings: 12

ewenmcneill · 2018-01-19T02:37:36Z

FTR the litex BIOS flashboot() change is currently only at ewen-naos-nz/litex on numato-elbert-v2, but plausibly could be merged into litex once it's been tested to not affect systems with MAIN_RAM_BASE set.

ewenmcneill · 2018-01-19T03:31:26Z

Based on hints on #timvideos IRC, apparently Spartan 3A has no PLL, and instead has a DCM (Digital Clock Manager) which needs completely different clock setup. This means clock setup for Elbert v2 will need rewriting from scratch rather than copying from Mimas v2 (Spartan 6, with PLL).

ewenmcneill · 2018-01-19T03:37:08Z

Tested litex BIOS change to avoid copying to main ram when there is no main ram on Mimas v2 / Arty A7 -- appears to work on those existing platforms. So created pull request -- enjoy-digital/litex#55 -- for that bit of the change so we can depend on it more easily.

ewenmcneill · 2018-01-19T06:10:39Z

FTR summarising discussion at Hackfest: it seems like the low end Xilinx Spartan 3A on the Numato Elbert v2 (Xilinx XC3S50A) is too small to fit even a cut down lm32 soft CPU, which means that it may not be a viable target for litex, even after clock issues are resolved. Ie, this might be a dead end, although possibly some of the work arounds to support "no external DRAM" might be useful for other dev boards with larger FPGA chips if they were cleaned up.

mithro · 2018-01-19T06:14:19Z

Yes, the "no external DRAM" is needed for a bunch of ice40, the pipistrello & probably others?

mithro · 2018-01-19T06:15:17Z

Gah, I did it again - I mean the Papillio not the Pipistrello....

ewenmcneill · 2018-02-08T03:52:00Z

@mithro IIRC the "no DRAM" development ended up being down elsewhere (by @rohitk-singh), so I don't think we're every going to merge this pull request as-is (and @rohitk-singh grabbed the relevant bits into his repo directly I believe). So perhaps close this pull request to avoid clutter?

rohitk-singh · 2018-02-08T04:05:55Z

Yup, I had cherry-picked commits related to fixing the firmware when not using SDSoC. There are some changes to litex also (enjoy-digital/litex#57) which haven't been merged yet (because haven't been tested yet).

mithro · 2018-02-09T16:29:52Z

Okay, closing this pull request.

* edid-decode changed from dcc8b83 to e6d15fd * e6d15fd - This project has moved <Adam Jackson> * litedram changed from 45da365 to 06f841d * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec> * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec> * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec> * d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec> |\ | * cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital> | |\ | | * 818c678 - update module settings to reflect latest changes <bunnie> | | * c9b8db5 - i think there's a missing "self" in the params <bunnie> * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec> |/ / * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec> * | 5715734 - frontend: add initial AXI support <Florent Kermarrec> * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec> * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec> |/ * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec> * 697eaaf - add board tuning parameters <bunnie> * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec> * 9401b92 - move sdram_init to litedram <Florent Kermarrec> * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec> * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec> * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec> * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec> * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec> * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec> * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec> * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec> * db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital> |\ | * 627cccd - Fix tCCD timing which watched the wrong command <> | * 16a852b - Revert "core/refresher: synchronize valid" <> | * a4be642 - Fix multiple timings ignored <> | * 771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <> | |\ | |/ |/| * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec> * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec> * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec> * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec> * | eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital> |\ \ | | * 3206985 - When auto-precharging assert track_close <> | | * 74279ea - Enable auto-precharge <> | |/ | * 03a2ad6 - Ensure out of order is on a per-bank basis <> | * 86b3e2d - Add reorder flag to the crossbar <> | * 77c513d - Merge upstream. UNTESTED <> | |\ | |/ |/| * | c28a754 - test: update <Florent Kermarrec> * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec> * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec> * | 26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital> |\ \ * \ \ 74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital> |\ \ \ | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell> | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie> * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec> * | | | 5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital> |\ \ \ \ | |/ / / |/| | | | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <> | | | * ed4be0b - Add write bank to out of order interface <> | | |/ | | * bfa1d6a - remove debug prints <> | | * 2fa2a6d - Initial implementation of out of order controller <> | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <> | |/ | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <> | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <> |/ * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec> * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec> * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec> * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec> * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec> * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec> * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec> * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec> * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec> * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec> * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec> * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec> * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec> * d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital> |\ | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <> | * d0fcfb1 - Auto-precharge now only fires when it needs to <> * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec> * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec> * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec> * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec> * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec> * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec> * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec> |/ * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec> * liteeth changed from 33afda7 to 24b0d2b * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec> * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec> * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec> * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec> * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec> * litepcie changed from 8bc328f to a97a691 * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec> * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec> * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec> * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec> * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec> * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec> * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec> * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec> * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec> * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec> * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec> * litesata changed from a559afb to 002cd25 * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 73cb6fa - example_designs: update <Florent Kermarrec> * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec> * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec> * 8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital> |\ | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held> | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held> * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litescope changed from 9d5e605 to f26e36e * f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital> |\ | * 71ffaa7 - add trigger depth option <bunnie> |/ * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec> * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec> * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec> * 3efaefa - example_designs: typo <Florent Kermarrec> * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec> * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec> * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec> * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec> * a269e67 - software: add rising/falling edge support <Florent Kermarrec> * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec> * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec> * 26a8b89 - example_designs: update <Florent Kermarrec> * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec> * liteusb changed from 23d6a68 to e841c56 * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litevideo changed from 9b4169d to 7b4240f * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital> * c704235 - additional debugging on capture <bunnie> * eab7078 - add data decoding to Terc4 decoder <bunnie> * eb263a8 - add ability to invert the HPD input <bunnie> * 7189562 - fix a default edid that works better with rpis <bunnie> * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie> * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie> * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie> * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie> * 447726f - add RGB input mode support to hdmi in <bunnie> * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie> * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie> * 9b3c93e - move BUFR->BUFG <bunnie> * 166dc57 - fix typo on naming <bunnie> * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie> * 784cc8c - changes needed for a basic genlock <bunnie> * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88 * 0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell> |\ | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones> * | ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell> |\ \ | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones> | |/ * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec> * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec> * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec> * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec> * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec> * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec> * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec> * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec> * | 2eeccc50 - vexriscv: update <Florent Kermarrec> * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec> |/ * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec> * 4225c3b8 - update Vexriscv <Florent Kermarrec> * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec> * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec> * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec> * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec> * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec> * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec> * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec> * e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital> |\ | * 3c7890cd - Fix generating csr.csv file <Peter Gielda> |/ * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec> * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec> * 580efecc - picorv32: add reset signal <Florent Kermarrec> * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec> * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec> * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec> * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec> * 380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital> |\ | * fb145dac - tools: remove vexriscv_debug <Sean Cross> | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross> | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross> |/ * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec> * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec> * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec> * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec> * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec> * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec> * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec> * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec> * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec> * 55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital> |\ | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross> * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec> * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec> * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec> * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec> * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec> |/ * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec> * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec> * b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital> |\ | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross> |/ * e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital> |\ | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross> | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross> |/ * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec> * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec> * 6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital> |\ | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross> | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross> | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross> | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross> * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec> * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec> |/ * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec> * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec> * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec> * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec> * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec> * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec> * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec> * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec> * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec> * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec> * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec> * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec> * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec> * 78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital> |\ | * 74449929 - soc: bios: fix windows build <Sean Cross> |/ * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec> * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec> * c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital> |\ | * 7353197e - fix the vexriscv boot helper <bunnie> |/ * 5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital> |\ | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver> |/ * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec> * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec> * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec> * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990> * f60da4a5 - add VexRiscv submodule <Florent Kermarrec> * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec> * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec> * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec> * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec> * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec> * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec> * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec> * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5 * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera> * 2d37c78 - add indexed part select support <Robin Ole Heinemann> * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones> * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark> * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark> * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark> * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark> * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark> * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq> * 47f4c59 - typo <Sebastien Bourdeauducq> * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq> * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq> * cb171af - platform: support adding connectors <Sebastien Bourdeauducq> * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones> * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq> * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec> * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty> * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq> * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq> * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq> * df0ce4a - Update version in setup.py. <whitequark> * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison> * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison> * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison> * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison> * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison> * ede1c9e - Add _connectors to constructor <Caleb Jamison> * 20d28d4 - Removed extra field from _connector list <Caleb Jamison> * 02e80df - Add chipkit io to _connector list <Caleb Jamison> * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison> * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison> * 04a9914 - Arty A7 platform <Caleb Jamison> * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński> * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens> * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens> * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq> * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq> * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq> * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens> * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens> * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec> * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark> * e66f2df - Fix documentation link in README. <whitequark> * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark> * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones> * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones> * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec> * 9bc084a - Update .gitignore. <whitequark> * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark> * 02bccef - Fix breakage introduced in 2220222. <whitequark> * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark> * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark> * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens> * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens> * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens> * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens> * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq> * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig> * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig> * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq> * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq> Full submodule status -- e6d15fd33e2e81b483921cb23642dbd8f05e08d2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD) 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD) a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD) 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD) f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD) e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD) 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD) 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88) a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)

* edid-decode changed from e6d15fd to b2da151 * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil> * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil> * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil> * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil> * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil> * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil> * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil> * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil> * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil> * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil> * 7684918 - edid-decode: README: updates <Hans Verkuil> * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil> * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson> * litedram changed from 45da365 to 06f841d * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec> * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec> * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec> * d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec> |\ | * cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital> | |\ | | * 818c678 - update module settings to reflect latest changes <bunnie> | | * c9b8db5 - i think there's a missing "self" in the params <bunnie> * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec> |/ / * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec> * | 5715734 - frontend: add initial AXI support <Florent Kermarrec> * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec> * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec> |/ * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec> * 697eaaf - add board tuning parameters <bunnie> * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec> * 9401b92 - move sdram_init to litedram <Florent Kermarrec> * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec> * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec> * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec> * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec> * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec> * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec> * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec> * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec> * db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital> |\ | * 627cccd - Fix tCCD timing which watched the wrong command <> | * 16a852b - Revert "core/refresher: synchronize valid" <> | * a4be642 - Fix multiple timings ignored <> | * 771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <> | |\ | |/ |/| * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec> * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec> * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec> * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec> * | eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital> |\ \ | | * 3206985 - When auto-precharging assert track_close <> | | * 74279ea - Enable auto-precharge <> | |/ | * 03a2ad6 - Ensure out of order is on a per-bank basis <> | * 86b3e2d - Add reorder flag to the crossbar <> | * 77c513d - Merge upstream. UNTESTED <> | |\ | |/ |/| * | c28a754 - test: update <Florent Kermarrec> * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec> * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec> * | 26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital> |\ \ * \ \ 74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital> |\ \ \ | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell> | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie> * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec> * | | | 5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital> |\ \ \ \ | |/ / / |/| | | | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <> | | | * ed4be0b - Add write bank to out of order interface <> | | |/ | | * bfa1d6a - remove debug prints <> | | * 2fa2a6d - Initial implementation of out of order controller <> | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <> | |/ | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <> | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <> |/ * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec> * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec> * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec> * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec> * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec> * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec> * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec> * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec> * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec> * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec> * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec> * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec> * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec> * d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital> |\ | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <> | * d0fcfb1 - Auto-precharge now only fires when it needs to <> * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec> * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec> * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec> * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec> * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec> * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec> * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec> |/ * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec> * liteeth changed from 33afda7 to 24b0d2b * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec> * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec> * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec> * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec> * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec> * litepcie changed from 8bc328f to a97a691 * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec> * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec> * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec> * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec> * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec> * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec> * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec> * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec> * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec> * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec> * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec> * litesata changed from a559afb to 002cd25 * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 73cb6fa - example_designs: update <Florent Kermarrec> * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec> * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec> * 8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital> |\ | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held> | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held> * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litescope changed from 9d5e605 to f26e36e * f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital> |\ | * 71ffaa7 - add trigger depth option <bunnie> |/ * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec> * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec> * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec> * 3efaefa - example_designs: typo <Florent Kermarrec> * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec> * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec> * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec> * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec> * a269e67 - software: add rising/falling edge support <Florent Kermarrec> * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec> * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec> * 26a8b89 - example_designs: update <Florent Kermarrec> * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec> * liteusb changed from 23d6a68 to e841c56 * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litevideo changed from 9b4169d to 7b4240f * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital> * c704235 - additional debugging on capture <bunnie> * eab7078 - add data decoding to Terc4 decoder <bunnie> * eb263a8 - add ability to invert the HPD input <bunnie> * 7189562 - fix a default edid that works better with rpis <bunnie> * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie> * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie> * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie> * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie> * 447726f - add RGB input mode support to hdmi in <bunnie> * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie> * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie> * 9b3c93e - move BUFR->BUFG <bunnie> * 166dc57 - fix typo on naming <bunnie> * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie> * 784cc8c - changes needed for a basic genlock <bunnie> * litex changed from v0.1-319-gb7f7c8d1 to v0.1-421-g0074bb88 * 0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell> |\ | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones> * | ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell> |\ \ | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones> | |/ * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec> * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec> * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec> * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec> * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec> * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec> * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec> * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec> * | 2eeccc50 - vexriscv: update <Florent Kermarrec> * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec> |/ * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec> * 4225c3b8 - update Vexriscv <Florent Kermarrec> * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec> * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec> * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec> * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec> * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec> * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec> * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec> * e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital> |\ | * 3c7890cd - Fix generating csr.csv file <Peter Gielda> |/ * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec> * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec> * 580efecc - picorv32: add reset signal <Florent Kermarrec> * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec> * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec> * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec> * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec> * 380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital> |\ | * fb145dac - tools: remove vexriscv_debug <Sean Cross> | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross> | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross> |/ * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec> * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec> * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec> * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec> * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec> * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec> * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec> * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec> * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec> * 55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital> |\ | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross> * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec> * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec> * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec> * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec> * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec> |/ * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec> * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec> * b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital> |\ | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross> |/ * e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital> |\ | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross> | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross> |/ * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec> * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec> * 6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital> |\ | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross> | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross> | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross> | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross> * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec> * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec> |/ * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec> * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec> * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec> * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec> * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec> * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec> * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec> * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec> * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec> * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec> * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec> * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec> * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec> * 78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital> |\ | * 74449929 - soc: bios: fix windows build <Sean Cross> |/ * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec> * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec> * c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital> |\ | * 7353197e - fix the vexriscv boot helper <bunnie> |/ * 5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital> |\ | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver> |/ * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec> * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec> * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec> * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990> * f60da4a5 - add VexRiscv submodule <Florent Kermarrec> * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec> * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec> * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec> * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec> * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec> * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec> * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec> * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5 * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera> * 2d37c78 - add indexed part select support <Robin Ole Heinemann> * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones> * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark> * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark> * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark> * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark> * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark> * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq> * 47f4c59 - typo <Sebastien Bourdeauducq> * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq> * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq> * cb171af - platform: support adding connectors <Sebastien Bourdeauducq> * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones> * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq> * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec> * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty> * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq> * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq> * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq> * df0ce4a - Update version in setup.py. <whitequark> * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison> * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison> * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison> * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison> * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison> * ede1c9e - Add _connectors to constructor <Caleb Jamison> * 20d28d4 - Removed extra field from _connector list <Caleb Jamison> * 02e80df - Add chipkit io to _connector list <Caleb Jamison> * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison> * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison> * 04a9914 - Arty A7 platform <Caleb Jamison> * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński> * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens> * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens> * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq> * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq> * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq> * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens> * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens> * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec> * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark> * e66f2df - Fix documentation link in README. <whitequark> * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark> * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones> * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones> * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec> * 9bc084a - Update .gitignore. <whitequark> * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark> * 02bccef - Fix breakage introduced in 2220222. <whitequark> * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark> * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark> * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens> * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens> * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens> * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens> * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq> * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig> * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig> * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq> * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq> Full submodule status -- b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 06f841dc2a9db65469c18041a13d9f84568bb213 litedram (remotes/origin/HEAD) 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD) a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD) 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD) f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD) e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD) 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD) 0074bb888c0e3ed20e4b1641d26fbb9bf2d05f81 litex (v0.1-421-g0074bb88) a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)

* edid-decode changed from dcc8b83 to b2da151 * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil> * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil> * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil> * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil> * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil> * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil> * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil> * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil> * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil> * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil> * 7684918 - edid-decode: README: updates <Hans Verkuil> * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil> * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson> * litedram changed from 45da365 to 7a5ac75 * 7a5ac75 - test/test_axi: improve test_axi2native <Florent Kermarrec> * d53832d - frontend/axi: split LiteDRAMAXI2Native (write path and read path) <Florent Kermarrec> * c846b8b - frontend/axi: add burst support (fixed/incr) <Florent Kermarrec> * 3fa77c8 - phy/s6ddrphy: use cwl only for DDR3 <Florent Kermarrec> * d9b5bb7 - frontend/bist: support axi with addressing in bytes <Florent Kermarrec> * 1370617 - frontend/axi: addressing in bytes not internal dwords <Florent Kermarrec> * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec> * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec> * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec> * d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec> |\ | * cd330b4 - Merge pull request timvideos#28 from AlphamaxMedia/refactor-master <enjoy-digital> | |\ | | * 818c678 - update module settings to reflect latest changes <bunnie> | | * c9b8db5 - i think there's a missing "self" in the params <bunnie> * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec> |/ / * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec> * | 5715734 - frontend: add initial AXI support <Florent Kermarrec> * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec> * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec> |/ * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec> * 697eaaf - add board tuning parameters <bunnie> * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec> * 9401b92 - move sdram_init to litedram <Florent Kermarrec> * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec> * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec> * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec> * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec> * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec> * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec> * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec> * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec> * db4ec67 - Merge pull request timvideos#24 from JohnSully/AutoPrecharge <enjoy-digital> |\ | * 627cccd - Fix tCCD timing which watched the wrong command <> | * 16a852b - Revert "core/refresher: synchronize valid" <> | * a4be642 - Fix multiple timings ignored <> | * 771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <> | |\ | |/ |/| * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec> * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec> * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec> * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec> * | eeb57ad - Merge pull request timvideos#23 from JohnSully/outoforder <enjoy-digital> |\ \ | | * 3206985 - When auto-precharging assert track_close <> | | * 74279ea - Enable auto-precharge <> | |/ | * 03a2ad6 - Ensure out of order is on a per-bank basis <> | * 86b3e2d - Add reorder flag to the crossbar <> | * 77c513d - Merge upstream. UNTESTED <> | |\ | |/ |/| * | c28a754 - test: update <Florent Kermarrec> * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec> * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec> * | 26f3f01 - Merge pull request timvideos#21 from JohnSully/outoforder <enjoy-digital> |\ \ * \ \ 74c3c09 - Merge pull request timvideos#20 from bunnie/400mhz-pr <enjoy-digital> |\ \ \ | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell> | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie> * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec> * | | | 5d74eb2 - Merge pull request timvideos#19 from JohnSully/timing <enjoy-digital> |\ \ \ \ | |/ / / |/| | | | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <> | | | * ed4be0b - Add write bank to out of order interface <> | | |/ | | * bfa1d6a - remove debug prints <> | | * 2fa2a6d - Initial implementation of out of order controller <> | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <> | |/ | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <> | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <> |/ * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec> * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec> * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec> * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec> * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec> * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec> * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec> * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec> * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec> * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec> * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec> * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec> * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec> * d150e3b - Merge pull request timvideos#12 from JohnSully/master <enjoy-digital> |\ | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <> | * d0fcfb1 - Auto-precharge now only fires when it needs to <> * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec> * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec> * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec> * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec> * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec> * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec> * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec> |/ * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec> * liteeth changed from 33afda7 to 24b0d2b * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec> * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec> * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec> * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec> * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec> * litepcie changed from 8bc328f to a97a691 * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec> * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec> * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec> * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec> * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec> * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec> * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec> * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec> * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec> * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec> * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec> * litesata changed from a559afb to 002cd25 * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 73cb6fa - example_designs: update <Florent Kermarrec> * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec> * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec> * 8bdc28e - Merge pull request timvideos#14 from felixheld/crc <enjoy-digital> |\ | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held> | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held> * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litescope changed from 9d5e605 to f26e36e * f26e36e - Merge pull request timvideos#11 from xobs/add-trigger-depth <enjoy-digital> |\ | * 71ffaa7 - add trigger depth option <bunnie> |/ * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec> * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec> * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec> * 3efaefa - example_designs: typo <Florent Kermarrec> * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec> * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec> * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec> * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec> * a269e67 - software: add rising/falling edge support <Florent Kermarrec> * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec> * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec> * 26a8b89 - example_designs: update <Florent Kermarrec> * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec> * liteusb changed from 23d6a68 to e841c56 * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * litevideo changed from 9b4169d to 7b4240f * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec> * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec> * cb8cf59 - Merge pull request timvideos#19 from bunnie/terc4-data <enjoy-digital> * c704235 - additional debugging on capture <bunnie> * eab7078 - add data decoding to Terc4 decoder <bunnie> * eb263a8 - add ability to invert the HPD input <bunnie> * 7189562 - fix a default edid that works better with rpis <bunnie> * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie> * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie> * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie> * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie> * 447726f - add RGB input mode support to hdmi in <bunnie> * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie> * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie> * 9b3c93e - move BUFR->BUFG <bunnie> * 166dc57 - fix typo on naming <bunnie> * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie> * 784cc8c - changes needed for a basic genlock <bunnie> * litex changed from v0.1-319-gb7f7c8d1 to v0.1-423-g7a14b75c * 7a14b75c - Merge pull request timvideos#93 from phlipped/master <Tim Ansell> |\ | * 8b51c445 - Fix URL for liteUSB <phlipped> |/ * 0074bb88 - Merge pull request timvideos#91 from cr1901/ignore-fix <Tim Ansell> |\ | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones> * | ff908e40 - Merge pull request timvideos#92 from cr1901/l2-gate <Tim Ansell> |\ \ | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones> | |/ * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec> * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec> * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec> * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec> * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec> * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec> * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec> * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec> * | 2eeccc50 - vexriscv: update <Florent Kermarrec> * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec> |/ * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec> * 4225c3b8 - update Vexriscv <Florent Kermarrec> * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec> * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec> * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec> * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec> * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec> * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec> * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec> * e07ca057 - Merge pull request timvideos#86 from pgielda/patch-1 <enjoy-digital> |\ | * 3c7890cd - Fix generating csr.csv file <Peter Gielda> |/ * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec> * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec> * 580efecc - picorv32: add reset signal <Florent Kermarrec> * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec> * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec> * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec> * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec> * 380f8b96 - Merge pull request timvideos#81 from xobs/vexriscv-to-wishbone <enjoy-digital> |\ | * fb145dac - tools: remove vexriscv_debug <Sean Cross> | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross> | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross> |/ * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec> * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec> * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec> * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec> * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec> * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec> * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec> * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec> * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec> * 55dd58b0 - Merge pull request timvideos#80 from xobs/fix-vexriscv-csr-read <enjoy-digital> |\ | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross> * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec> * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec> * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec> * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec> * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec> * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec> |/ * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec> * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec> * b062d4dd - Merge pull request timvideos#79 from xobs/fix-vexriscv-data-read <enjoy-digital> |\ | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross> |/ * e35be26e - Merge pull request timvideos#78 from xobs/vexriscv_debug_bridge <enjoy-digital> |\ | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross> | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross> |/ * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec> * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec> * 6068f6ce - Merge pull request timvideos#77 from xobs/debug-vexriscv-enjoy <enjoy-digital> |\ | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross> | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross> | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross> | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross> * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec> * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec> |/ * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec> * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec> * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec> * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec> * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec> * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec> * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec> * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec> * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec> * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec> * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec> * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec> * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec> * 78639fa9 - Merge pull request timvideos#75 from xobs/bios-windows-build <enjoy-digital> |\ | * 74449929 - soc: bios: fix windows build <Sean Cross> |/ * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec> * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec> * c534250c - Merge pull request timvideos#72 from bunnie/fix_riscv_boothelper <enjoy-digital> |\ | * 7353197e - fix the vexriscv boot helper <bunnie> |/ * 5ab4282e - Merge pull request timvideos#71 from DeanoC/master <enjoy-digital> |\ | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver> |/ * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec> * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec> * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec> * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990> * f60da4a5 - add VexRiscv submodule <Florent Kermarrec> * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec> * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec> * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec> * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec> * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec> * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec> * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec> * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5 * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera> * 2d37c78 - add indexed part select support <Robin Ole Heinemann> * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (timvideos#111) <William D. Jones> * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark> * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark> * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark> * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark> * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark> * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq> * 47f4c59 - typo <Sebastien Bourdeauducq> * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq> * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq> * cb171af - platform: support adding connectors <Sebastien Bourdeauducq> * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (timvideos#88) <William D. Jones> * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq> * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec> * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty> * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq> * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq> * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq> * df0ce4a - Update version in setup.py. <whitequark> * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison> * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison> * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison> * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison> * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison> * ede1c9e - Add _connectors to constructor <Caleb Jamison> * 20d28d4 - Removed extra field from _connector list <Caleb Jamison> * 02e80df - Add chipkit io to _connector list <Caleb Jamison> * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison> * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison> * 04a9914 - Arty A7 platform <Caleb Jamison> * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński> * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens> * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens> * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq> * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq> * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq> * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens> * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens> * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec> * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec> * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark> * e66f2df - Fix documentation link in README. <whitequark> * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark> * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones> * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones> * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec> * 9bc084a - Update .gitignore. <whitequark> * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark> * 02bccef - Fix breakage introduced in 2220222. <whitequark> * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark> * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark> * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens> * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens> * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens> * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens> * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq> * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (timvideos#96) <Adam Greig> * c14a1e4 - Add MyStorm BlackIce I and II platforms (timvideos#95) <Adam Greig> * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq> * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq> Full submodule status -- b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 7a5ac75e2295dcf15f83df966244f30154a8f662 litedram (remotes/origin/HEAD) 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD) a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD) 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD) f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD) e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD) 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD) 7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef litex (v0.1-423-g7a14b75c) a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)

* litedram changed from 7a5ac75 to 461b076 * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec> * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec> * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec> * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec> * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec> * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec> * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec> * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec> * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec> * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec> * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec> * 412e9a5 - Merge pull request timvideos#38 from enjoy-digital/multirank <enjoy-digital> |\ | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec> | * d4f434d - dfii: send command to all ranks <Florent Kermarrec> | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec> * | d9c2430 - Merge pull request timvideos#36 from JohnSully/timing_1 <enjoy-digital> |\ \ | |/ |/| | * efd7a47 - Fix failing timing <> * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec> |/ * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec> * 1fa73e4 - test: update <Florent Kermarrec> * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec> * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec> * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec> * 700f76c - frontend/axi: add resp signals <Florent Kermarrec> * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec> * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec> * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec> * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec> * ebba39d - README: update <Florent Kermarrec> * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec> * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec> * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec> * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec> * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec> * dce4ede - README: update <Florent Kermarrec> * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec> * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec> * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec> * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec> * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec> * bc8a9ce - README: update <Florent Kermarrec> * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec> * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec> * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec> * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec> * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec> * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec> * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec> * d5d6737 - frontend/axi: fix read id <Florent Kermarrec> * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec> * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec> * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec> * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec> * liteeth changed from 24b0d2b to 5106bcd * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec> * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec> * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec> * litepcie changed from a97a691 to 3e8de2d * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec> * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec> * litesata changed from 002cd25 to fb72044 * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec> * litescope changed from f26e36e to 686db4f * 686db4f - Merge pull request timvideos#12 from xobs/default-length <enjoy-digital> |\ | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross> |/ * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec> * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec> * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec> * liteusb changed from e841c56 to 0a9110f * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec> * litevideo changed from 7b4240f to 13d85a1 * 13d85a1 - README: update <Florent Kermarrec> * litex changed from 7a14b75c to 9c6f76f1 * 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec> * a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec> * 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec> * 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec> * 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec> * df3f003e - soc_sdram: update with litedram <Florent Kermarrec> * bebc667d - Merge pull request timvideos#99 from cr1901/mk-copy-main-ram <enjoy-digital> |\ | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones> * | 69716852 - Merge pull request timvideos#100 from cr1901/tinyprog-fix <enjoy-digital> |\ \ | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones> | |/ * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec> * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec> * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen> * | d9d0320d - Merge pull request timvideos#98 from jfng/fix_typo <enjoy-digital> |\ \ | * | 22c01313 - fix typo and unused include <Jean-François Nguyen> |/ / * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec> * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec> * | 8f377307 - add Minerva support <Jean-François Nguyen> * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec> |/ * c5a2d6f3 - Merge pull request timvideos#96 from cr1901/tinyfpga_bx <Tim Ansell> |\ | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * | 3cb754da - Merge pull request timvideos#95 from cr1901/lm32-lite <Tim Ansell> |\ \ | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. <William D. Jones> | |/ * | 28cd2da2 - README: update <Florent Kermarrec> |/ * 05c7b9da - Merge pull request timvideos#94 from cr1901/nextpnr <enjoy-digital> * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones> * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-166-g2a7e33e * 2a7e33e - Emit `default_nettype none. <David Craven> * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens> * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (timvideos#124) <William D. Jones> Full submodule status -- b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) 461b076624ae497d49f4498922f3bdcd7e80995c litedram (remotes/origin/HEAD) 5106bcdc0c96e78d953694e8bb86a7feb60d474d liteeth (remotes/origin/HEAD) 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD) fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD) 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 9c6f76f18c17cf1d20bb2622fa17daefbb42d5ad litex (remotes/origin/HEAD) 2a7e33e9a46a4dd764faa1694b93e3223e716577 migen (0.6.dev-166-g2a7e33e)

* edid-decode changed from b2da151 to 5eeb151 * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB <Hans Verkuil> * litedram changed from 7a5ac75 to e5696ad * e5696ad - frontend/ecc: add enable csr <Florent Kermarrec> * e6ef89a - frontend/axi: optimize burst2beat timings <Florent Kermarrec> * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings <Florent Kermarrec> * 041817d - frontend/ecc: use csr instead of signal for control <Florent Kermarrec> * b145b0c - frontend/axi: fix write response implementation <Florent Kermarrec> * d23dbf6 - phy: add nranks to all phys <Florent Kermarrec> * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec> * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec> * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec> * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec> * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec> * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec> * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec> * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec> * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec> * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec> * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec> * 412e9a5 - Merge pull request timvideos#38 from enjoy-digital/multirank <enjoy-digital> |\ | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec> | * d4f434d - dfii: send command to all ranks <Florent Kermarrec> | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec> * | d9c2430 - Merge pull request timvideos#36 from JohnSully/timing_1 <enjoy-digital> |\ \ | |/ |/| | * efd7a47 - Fix failing timing <> * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec> |/ * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec> * 1fa73e4 - test: update <Florent Kermarrec> * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec> * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec> * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec> * 700f76c - frontend/axi: add resp signals <Florent Kermarrec> * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec> * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec> * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec> * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec> * ebba39d - README: update <Florent Kermarrec> * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec> * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec> * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec> * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec> * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec> * dce4ede - README: update <Florent Kermarrec> * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec> * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec> * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec> * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec> * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec> * bc8a9ce - README: update <Florent Kermarrec> * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec> * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec> * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec> * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec> * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec> * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec> * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec> * d5d6737 - frontend/axi: fix read id <Florent Kermarrec> * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec> * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec> * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec> * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec> * liteeth changed from 24b0d2b to 3d86844 * 3d86844 - core/mac/sram: fix code refactoring <Florent Kermarrec> * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec> * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec> * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec> * litepcie changed from a97a691 to 3e8de2d * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec> * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec> * litesata changed from 002cd25 to fb72044 * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec> * litescope changed from f26e36e to 686db4f * 686db4f - Merge pull request timvideos#12 from xobs/default-length <enjoy-digital> |\ | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross> |/ * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec> * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec> * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec> * liteusb changed from e841c56 to 0a9110f * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec> * litevideo changed from 7b4240f to 13d85a1 * 13d85a1 - README: update <Florent Kermarrec> * litex changed from 7a14b75c to 537b0e90 * 537b0e90 - Merge pull request timvideos#101 from cr1901/icestorm-migen-pull <enjoy-digital> |\ | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. <William D. Jones> * | 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec> * | a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec> * | 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec> * | 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec> * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec> * | df3f003e - soc_sdram: update with litedram <Florent Kermarrec> |/ * bebc667d - Merge pull request timvideos#99 from cr1901/mk-copy-main-ram <enjoy-digital> |\ | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones> * | 69716852 - Merge pull request timvideos#100 from cr1901/tinyprog-fix <enjoy-digital> |\ \ | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones> | |/ * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec> * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec> * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen> * | d9d0320d - Merge pull request timvideos#98 from jfng/fix_typo <enjoy-digital> |\ \ | * | 22c01313 - fix typo and unused include <Jean-François Nguyen> |/ / * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec> * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec> * | 8f377307 - add Minerva support <Jean-François Nguyen> * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec> |/ * c5a2d6f3 - Merge pull request timvideos#96 from cr1901/tinyfpga_bx <Tim Ansell> |\ | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * | 3cb754da - Merge pull request timvideos#95 from cr1901/lm32-lite <Tim Ansell> |\ \ | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. <William D. Jones> | |/ * | 28cd2da2 - README: update <Florent Kermarrec> |/ * 05c7b9da - Merge pull request timvideos#94 from cr1901/nextpnr <enjoy-digital> * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones> * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. <whitequark> * b2740d9 - build.lattice.icestorm: write build script even on dry run. <whitequark> * 2a7e33e - Emit `default_nettype none. <David Craven> * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens> * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (timvideos#124) <William D. Jones> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) e5696ad3ef516df8033149f748e5ede93b54b57d litedram (remotes/origin/HEAD) 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD) 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD) fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD) 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD) ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)

* edid-decode changed from b2da151 to 5eeb151 * 5eeb151 - edid-decode: replace AdobeYCC/RGB by opYCC/RGB <Hans Verkuil> * litedram changed from 7a5ac75 to ea1ac4d * ea1ac4d - s6ddrphy: Pass missing nranks parameter. <Tim 'mithro' Ansell> * e5696ad - frontend/ecc: add enable csr <Florent Kermarrec> * e6ef89a - frontend/axi: optimize burst2beat timings <Florent Kermarrec> * 6941285 - frontend/ecc: split Write/Read path and add buffer to improve timings <Florent Kermarrec> * 041817d - frontend/ecc: use csr instead of signal for control <Florent Kermarrec> * b145b0c - frontend/axi: fix write response implementation <Florent Kermarrec> * d23dbf6 - phy: add nranks to all phys <Florent Kermarrec> * 461b076 - frontend/ecc: add ecc adapter <Florent Kermarrec> * c84b587 - frontend: add initial ecc code (still need to be integrated) <Florent Kermarrec> * a8d2672 - phy/s7ddrphy_halfrate_bl8: don't generate dqs pre/post-amble, needs simulation <Florent Kermarrec> * 5719d71 - phy/s7ddrphy_halfrate_bl8: fix cs_n <Florent Kermarrec> * 36fa324 - core/multiplexer: fix regression (introduced by multirank support) <Florent Kermarrec> * 42d0e5b - core/multiplexer: add more information on odt fixme <Florent Kermarrec> * 919b756 - phy/model: pass nranks to Interface <Florent Kermarrec> * f5c7b61 - multirank: set default nranks to 1 if not specified <Florent Kermarrec> * f3d403f - s7ddrphy: fix typo (reset_n --> cs_n) <Florent Kermarrec> * 37f1dec - multirank: one cs_n/cke/odt/clk per rank <Florent Kermarrec> * 3e17d18 - phy: add halfrate_bl8 variant for s7ddrphy <Florent Kermarrec> * 412e9a5 - Merge pull request timvideos#38 from enjoy-digital/multirank <enjoy-digital> |\ | * 8ddc6c7 - drive odt of all ranks, fixes and test non regression with 1 rank <Florent Kermarrec> | * d4f434d - dfii: send command to all ranks <Florent Kermarrec> | * b1c2739 - initial multirank support (nbankmachines = nranks * (2**bankbits)) <Florent Kermarrec> * | d9c2430 - Merge pull request timvideos#36 from JohnSully/timing_1 <enjoy-digital> |\ \ | |/ |/| | * efd7a47 - Fix failing timing <> * | cc481be - examples: add sdram_rank_nb and user_ports_id_width <Florent Kermarrec> |/ * 849b1f6 - frontend/axi: generate rlast signal <Florent Kermarrec> * 1fa73e4 - test: update <Florent Kermarrec> * 7b61b68 - sdram_init: min value for wr is 5 <Florent Kermarrec> * 1652ab9 - examples/litedram_gen: fix address width of axi ports (addressing in bytes not words) <Florent Kermarrec> * 1e64b7f - examples/litedram_gen: expose resp signals to user <Florent Kermarrec> * 700f76c - frontend/axi: add resp signals <Florent Kermarrec> * 47fed1b - frontend/axi: add last limitation <Florent Kermarrec> * de69867 - examples/litedram_gen: expose last signals to user <Florent Kermarrec> * e8bd782 - examples/litedram_gen: expose burst signals to user <Florent Kermarrec> * e1598ce - phy/s7ddrphy: fix BL8 assert <Florent Kermarrec> * ebba39d - README: update <Florent Kermarrec> * e528e92 - phy/s7ddrphy: add assertion to avoid generating 1:2 controller with DDR3 (needs BL8 support in the PHY) <Florent Kermarrec> * 6017e7a - phy/s7ddrphy: fix dqs_sys_latency for DDR2 <Florent Kermarrec> * 7b42739 - phy/s7ddrphy: simplify cmd/dat phases computation and remove restrictions. <Florent Kermarrec> * 6148618 - phy/s7ddrphy: use dict in get_cl_cw function <Florent Kermarrec> * 5e4dca9 - add examples with standalone cores for arty and genesys2 <Florent Kermarrec> * dce4ede - README: update <Florent Kermarrec> * f6797a1 - test/test_axi: add burst wrap test and fix code <Florent Kermarrec> * 47988d8 - frontend/axi: remove alignment limitation since we are in fact supporting unaligned transfers as described in the specification. <Florent Kermarrec> * 6cc42c6 - frontend/axi: add wrap burst support <Florent Kermarrec> * 9c729ae - core: replace adr with addr on native interface (closer to AXI and allow some simplifications) <Florent Kermarrec> * 0506708 - core/controller: remove simulation workaround <Florent Kermarrec> * bc8a9ce - README: update <Florent Kermarrec> * 6f7ae84 - frontend/axi: increase default depth of buffers to improve performance <Florent Kermarrec> * ed7eef1 - phy/s7ddrphy: fix preamble/posamble latency when with_odelay (-1 since dqs clk is not shifted) <Florent Kermarrec> * c37d3af - frontend/bist: only keep random datas (we can generate random addresses with control) <Florent Kermarrec> * b1e734b - frontend/bist: only use cdc on registers if needed (ie not in sys clock domain) <Florent Kermarrec> * 92c8513 - frontend/axi: add buffer to accept command before converting burst to beats <Florent Kermarrec> * c15c474 - test/test_axi: split reads/writes generators <Florent Kermarrec> * 95cb7cd - test: rename read/write generators to handlers <Florent Kermarrec> * d5d6737 - frontend/axi: fix read id <Florent Kermarrec> * 10229d1 - test/test_axi: improve test_axi2native <Florent Kermarrec> * 295f016 - frontend/axi: add features/limitations <Florent Kermarrec> * 6a46ea3 - test/test_bist: add generator test, remove async test <Florent Kermarrec> * 7677a85 - core/bankmachine: expose cmd_buffer_buffered param and small cleanup <Florent Kermarrec> * liteeth changed from 24b0d2b to 3d86844 * 3d86844 - core/mac/sram: fix code refactoring <Florent Kermarrec> * 5106bcd - core/mac/sram: simplify last_be code <Florent Kermarrec> * ce72e34 - core/mac: pass endianness and use if for last_be gen/check <Florent Kermarrec> * 94af3d6 - README: update and rename example_designs to examples <Florent Kermarrec> * litepcie changed from a97a691 to 3e8de2d * 3e8de2d - phy/s7pciephy: remove clock constraints from phy <Florent Kermarrec> * 6f2d97a - README: update and rename example_designs to example <Florent Kermarrec> * litesata changed from 002cd25 to fb72044 * fb72044 - README: update and rename example_designs to examples <Florent Kermarrec> * litescope changed from f26e36e to 686db4f * 686db4f - Merge pull request timvideos#12 from xobs/default-length <enjoy-digital> |\ | * 4f8b9a3 - analyzer-driver: use default depth from config <Sean Cross> |/ * 7c1c62e - README: update and rename example_designs to examples <Florent Kermarrec> * 3567b68 - dump/vcd: fix code generation <Florent Kermarrec> * 182b683 - core: change cd parameter to clock_domain (keep retro compatibility for now) <Florent Kermarrec> * liteusb changed from e841c56 to 0a9110f * 0a9110f - README: update and rename example_designs to examples <Florent Kermarrec> * litevideo changed from 7b4240f to 13d85a1 * 13d85a1 - README: update <Florent Kermarrec> * litex changed from 7a14b75c to 537b0e90 * 537b0e90 - Merge pull request timvideos#101 from cr1901/icestorm-migen-pull <enjoy-digital> |\ | * 5c83c881 - Pull in b2740d9 from Migen. nextpnr now default, write out build scripts on dry run. <William D. Jones> * | 9c6f76f1 - bios/sdram: mode sdhw() <Florent Kermarrec> * | a44bedd5 - bios/sdram: add missing #ifdef <Florent Kermarrec> * | 0e68daeb - targets: self.pll_sys --> pll_sys <Florent Kermarrec> * | 1468b9f3 - bios/sdram: show all read scans when failing. <Florent Kermarrec> * | 07e4c183 - cpu/lm32: re-enable multiplier/divider in minimal variant (does not seem to work correctly on hardware otherwise) <Florent Kermarrec> * | df3f003e - soc_sdram: update with litedram <Florent Kermarrec> |/ * bebc667d - Merge pull request timvideos#99 from cr1901/mk-copy-main-ram <enjoy-digital> |\ | * bd70ba27 - Add COPY_TO_MAIN_RAM generated Makefile variable to distinguish systems with/without main_ram region. <William D. Jones> * | 69716852 - Merge pull request timvideos#100 from cr1901/tinyprog-fix <enjoy-digital> |\ \ | * | c812321a - lattice/programmer: Use --program-image option with tinyprog if address is given. <William D. Jones> | |/ * | 12a89447 - soc_sdram: revert vivado l2 cache workaround (still seems to cause issues on some cases...) <Florent Kermarrec> * | 2b786065 - targets: pass endianness to LiteEThMAC, tftp working with RISC-V, still need to fix txlen <Florent Kermarrec> * | 26963d62 - libnet/microudp: (WIP) fix endianness issues <Jean-François Nguyen> * | d9d0320d - Merge pull request timvideos#98 from jfng/fix_typo <enjoy-digital> |\ \ | * | 22c01313 - fix typo and unused include <Jean-François Nguyen> |/ / * | fb24ac0e - cpu/minerva: add workaround on import until code is released <Florent Kermarrec> * | 9cfae4df - setup.py: create litex_sim exec to ease simulation <Florent Kermarrec> * | 8f377307 - add Minerva support <Jean-François Nguyen> * | 1944289e - litex_server: update pcie and remove bar_size parameter <Florent Kermarrec> |/ * c5a2d6f3 - Merge pull request timvideos#96 from cr1901/tinyfpga_bx <Tim Ansell> |\ | * 29492624 - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * | 3cb754da - Merge pull request timvideos#95 from cr1901/lm32-lite <Tim Ansell> |\ \ | * | ed507d61 - Add lm32 "lite" variant, remove mult/div from "minimal" and update compiler flags accordingly. <William D. Jones> | |/ * | 28cd2da2 - README: update <Florent Kermarrec> |/ * 05c7b9da - Merge pull request timvideos#94 from cr1901/nextpnr <enjoy-digital> * 7af89efc - lattice/icestorm: Add nextpnr pnr as alternate pnr tool. <William D. Jones> * migen changed from 0.6.dev-162-ga6082d5 to 0.6.dev-168-gca0df1c * ca0df1c - build.platforms: add ice40_up5k_b_evn platform. <whitequark> * b2740d9 - build.lattice.icestorm: write build script even on dry run. <whitequark> * 2a7e33e - Emit `default_nettype none. <David Craven> * cff127d - build/platforms: Add TinyFPGA BX board and programmer. <William D. Jones> * 97e2651 - kasli: set USERID and USR_ACCESS <Robert Jördens> * 58894fb - lattice/icestorm: Add nextpnr as alternate pnr tool. (timvideos#124) <William D. Jones> Full submodule status -- 5eeb151a748788666534d6ea3da07f90400d24c2 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) ea1ac4d6d72ecb9a65fb884857db8ba6851f3230 litedram (heads/s6-rank-fix) 3d868449e9c38a00524cff8ed2bf5dec2fc0d858 liteeth (remotes/origin/HEAD) 3e8de2d1ef347a1fdfbd01601b1bbdc4558dd90a litepcie (remotes/origin/HEAD) fb72044dabd121b4643a936b21ca3bf3aed75499 litesata (remotes/origin/HEAD) 686db4f3cd71bade8dd777d112e66797662f5bad litescope (remotes/origin/HEAD) 0a9110f901182a1233cc4e64b6e39175f6784621 liteusb (remotes/origin/HEAD) 13d85a1fe360678bebd57c55f1b35988c655ae95 litevideo (remotes/origin/HEAD) 537b0e9058e6a5b77f434f46f3a56849c82064bd litex (remotes/origin/HEAD) ca0df1c148950213ff0551a8ec7c188a5910906e migen (0.6.dev-168-gca0df1c)

* edid-decode changed from 42f5fa4 to 7d26052 * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil> * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao> * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil> * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil> * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil> * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil> * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil> * flash_proxies changed from 1c21ee4 to 01d8f81 * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq> * litedram changed from 6c53996 to 5d1a984 * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec> * d647abd - gen: fix with_wishbone <Florent Kermarrec> * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec> * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec> * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec> * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec> * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt> * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt> * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec> * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec> * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec> * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec> * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec> * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec> * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec> * 40b4c62 - test/test_init: fix <Florent Kermarrec> * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec> * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec> * 6e176d4 - init: split by memtype <Florent Kermarrec> * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec> * bf5883c - rename sdram_init to init <Florent Kermarrec> * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec> * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec> * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec> * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec> * 00ecb87 - gen: add separators <Florent Kermarrec> * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec> * f678efa - travis: add pyyaml <Florent Kermarrec> * 8861d80 - Merge pull request timvideos#91 from sd-fritze/master <enjoy-digital> |\ | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf> |/ * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec> * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec> * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec> * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec> * 602ff8b - examples: switch to YAML config files <Florent Kermarrec> * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec> * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec> * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec> * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec> * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec> * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec> * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec> * f0592ff - core/refresher: add comments <Florent Kermarrec> * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec> * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec> * liteeth changed from ad187d3 to 4d9e74f * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec> * 4bc79ce - examples/targets/core: update <Florent Kermarrec> * cd0eaa9 - Merge pull request timvideos#19 from jersey99/master <enjoy-digital> * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla> * litepcie changed from 71c9a3a to 47e76f4 * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec> * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec> * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec> * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec> * litescope changed from 9e3b9d8 to 7a9fa9d * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec> * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec> * 69a8df0 - Merge pull request timvideos#14 from DurandA/master <enjoy-digital> * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand> * litevideo changed from 98e145f to 49bafa4 * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec> * litex changed from e637aa65 to b627a8fe * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec> * cc245fc8 - Merge pull request timvideos#275 from pcotret/patch-1 <enjoy-digital> |\ | * e923a88d - Update README (related to issue timvideos#273) <Pascal Cotret> * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec> * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec> * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec> * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec> * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec> |/ * e8b90e80 - Merge pull request timvideos#274 from gsomlo/gls-shadow-base <enjoy-digital> |\ | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo> |/ * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec> * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec> * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec> * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec> * 2dfe7441 - Merge pull request timvideos#271 from gsomlo/gls-yosys-nowidelut <enjoy-digital> |\ | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo> * | c954ff0c - Merge pull request timvideos#272 from sergachev/fix-comments <enjoy-digital> |\ \ | |/ |/| | * 2f7bd971 - fix comments <Ilia Sergachev> * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec> |/ * 960b25a5 - Merge pull request timvideos#270 from gsomlo/gls-csr-upper <enjoy-digital> |\ | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo> * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec> * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec> * | 4bb2827e - Merge pull request timvideos#269 from antmicro/rework_icap <enjoy-digital> |\ \ | |/ |/| | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski> * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec> * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec> * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec> * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec> * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec> * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec> * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec> * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec> * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec> * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec> * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec> * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec> * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec> * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec> * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec> * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec> * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec> * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec> * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec> * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec> * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec> * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec> * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec> * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec> * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec> * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec> * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec> * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec> * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec> * | a4069fc8 - add SERV submodule <Florent Kermarrec> * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec> * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec> * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec> * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec> * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec> * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec> * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec> * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec> * | 836d5b88 - Merge pull request timvideos#266 from xobs/add-moduledoc-autodoc <enjoy-digital> |\ \ | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross> | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross> * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec> * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt> * | | 742da31b - Merge pull request timvideos#264 from antmicro/mor1kx_linux <enjoy-digital> |\ \ \ | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski> | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski> * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec> * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec> |/ / / * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec> * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec> * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec> * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec> * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt> * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt> * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt> |/ / * | 8b7d8217 - Merge pull request timvideos#263 from xobs/spi-flash-csrfield <enjoy-digital> |\ \ | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross> |/ / * | 4f659ba4 - Merge pull request timvideos#262 from jersey99/master <enjoy-digital> |\ \ | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla> |/ / * | 430fee4d - Merge pull request timvideos#261 from xobs/event-documentation <enjoy-digital> |\ \ | |/ |/| | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross> |/ * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec> * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec> * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec> * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec> * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec> * f1139c36 - Merge pull request timvideos#259 from xobs/document-timer <enjoy-digital> |\ | * cb7d941a - timer: add documentation <Sean Cross> |/ * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec> * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec> * 3dc8d294 - Merge pull request timvideos#257 from enjoy-digital/csr_fields <enjoy-digital> |\ | * 9bda614a - csr: update copyrights <Florent Kermarrec> | * 29134cc6 - csr: more documentation <Florent Kermarrec> | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec> | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec> | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec> | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec> | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec> | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec> | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec> |/ * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec> * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec> * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec> * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec> * cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec> |\ | * a7b5c185 - Merge pull request timvideos#255 from sergachev/fix-crc32 <enjoy-digital> | |\ | | * 2400f0f4 - fix crc32 <Ilia Sergachev> | |/ * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec> |/ * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec> * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec> * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec> * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec> * 2638393b - soc_zynq: fix indent <Florent Kermarrec> * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec> * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec> * 6f150a56 - Merge pull request timvideos#254 from mithro/crc-smaller <enjoy-digital> |\ | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell> | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell> | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross> | * a59d0efc - libbase: crc32: add smaller version <Sean Cross> * | 27c334d4 - Merge pull request timvideos#252 from mithro/only-change-on-contents <Tim Ansell> |\ \ | |/ |/| | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell> |/ * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec> * 19d3acfc - Merge pull request timvideos#251 from micro-FPGA/master <enjoy-digital> |\ | * fb00ee85 - Create atlantic.py <Antti Lukats> | * 92e5b4b2 - Merge pull request #2 from enjoy-digital/master <Antti Lukats> | |\ | * | f47e4978 - libero enable enhanced constraints <Antti Lukats> * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec> * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec> * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec> * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec> * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec> * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec> * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec> * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec> * | | d79cd87d - Merge pull request timvideos#246 from gsomlo/gls-native-rv64 <enjoy-digital> |\ \ \ | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo> |/ / / * | | d36f1fb7 - Merge pull request timvideos#244 from atommann/master <enjoy-digital> |\ \ \ | |_|/ |/| | | * | a45dbee5 - changing http to https <atommann> | * | 1d957d7a - Update .gitmodules <atommann> * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec> * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats> | |/ |/| * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec> * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec> * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec> * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec> * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec> * | f6638ded - Merge pull request timvideos#243 from sergachev/master <enjoy-digital> |\ \ | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev> * | | ccc2cbd9 - Merge pull request timvideos#241 from railnova/zynq <enjoy-digital> |\ \ \ | |/ / |/| | | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset> |/ / * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec> * | 383c05e2 - Merge pull request timvideos#240 from danielkucera/patch-1 <enjoy-digital> |\ \ | |/ |/| | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera> |/ * 2b815f70 - Merge pull request timvideos#235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital> |\ | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo> |/ * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec> * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec> * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec> * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec> * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec> * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec> * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec> * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec> * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec> * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec> * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec> * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec> * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec> * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec> * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec> * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec> * 236070fd - cores: -x on spi.py <Florent Kermarrec> * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec> * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec> * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec> * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec> * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec> * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec> * ae00482d - Merge pull request timvideos#223 from sergachev/master <enjoy-digital> * fdb119cb - support vivado incremental implementation <Ilia Sergachev> * litex-renode changed from a57aa47 to b3fdb9b * b3fdb9b - Merge pull request timvideos#13 from antmicro/xip_flash <Tim Ansell> |\ | * 2080118 - Generate LiteX SPI Flash with underlying memory <Mateusz Holenko> |/ * e4ebebf - generate-renode-scripts: be sure kind/variant are in uppercase <Florent Kermarrec> * 4c072c8 - litex directory: add missing __init__.py <Florent Kermarrec> * dcd3fd8 - Extract HDMI2USB mocserver code to a separate file <Mateusz Holenko> * 2bb663f - Extract LiteX configuration parser <Mateusz Holenko> * e3c51a4 - Make this repo a proper python package <Mateusz Holenko> * 30d044e - Merge pull request timvideos#11 from CarlFK/master <Mateusz Hołenko> |\ | * e2f6a00 - adds --json-file and code to create a json file for the moc server. <Carl Karsten> | * b581fd6 - make a main() and parse_args() <Carl Karsten> * | eaeae9b - Merge pull request timvideos#12 from antmicro/rename_litex_spi_flash <Tim Ansell> |\ \ | |/ |/| | * 401babc - Adapt to LiteX_SPI model rename <Mateusz Holenko> |/ * 301b0fd - Merge pull request timvideos#10 from antmicro/fix_gdb <Tim Ansell> |\ | * 8a3a55b - Adapt to GDB API changes in Renode <Mateusz Holenko> * 3a4943c - Merge pull request timvideos#9 from antmicro/6-improve_readme <Tim Ansell> * cccefd4 - [timvideos#6] Improve the README. <Mateusz Holenko> * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq> * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq> * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq> * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq> * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq> * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq> * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq> * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq> * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq> * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq> * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq> * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq> * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq> * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz> * f4fcd10 - fix previous commit <Sebastien Bourdeauducq> * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq> Full submodule status -- 7d26052f7245664df96079845601ced5335fb2d7 edid-decode (remotes/origin/HEAD) 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD) 5d1a9847aa805034e58eabf376e2807bfed7b133 litedram (remotes/origin/HEAD) 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD) 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD) db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master) 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD) 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master) 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD) b627a8fe71b55f1987a9cd5181da14cddd3203c1 litex (remotes/origin/HEAD) b3fdb9b litex-renode (remotes/origin/HEAD) 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)

Adapt to LiteX_SPI model rename

ewenmcneill added 2 commits January 18, 2018 16:59

scripts/download-env.sh: install elbertconfig.py

e8f6bc4

platforms/elbertv2.py: Elbert V2 board definition

ec33d2f

First attempt; hand translated from Numato UCF file; currently untested.

probot-autolabeler bot added the level-infrastructure label Jan 18, 2018

probot-autolabeler bot added the hdmi2*** label Jan 18, 2018

ewenmcneill added 4 commits January 19, 2018 12:42

litex: BIOS: Flashboot without main ram

b89e7b2

probot-autolabeler bot added level-infrastructure firmware-softcpu level-firmware labels Jan 19, 2018

firmware/linker.fd: Swap 0x100 offset to 0x08

d169bbb

probot-autolabeler bot added firmware-softcpu hdmi2*** level-firmware level-infrastructure labels Jan 19, 2018

mithro closed this Feb 9, 2018

mateusz-holenko pushed a commit to antmicro/litex-buildenv that referenced this pull request Oct 21, 2019

Merge pull request timvideos#12 from antmicro/rename_litex_spi_flash

eaeae9b

Adapt to LiteX_SPI model rename

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WIP: Numato Elbert V2 support #12

WIP: Numato Elbert V2 support #12

mithro commented Jan 18, 2018

ewenmcneill commented Jan 18, 2018

ewenmcneill commented Jan 19, 2018

ewenmcneill commented Jan 19, 2018

ewenmcneill commented Jan 19, 2018

ewenmcneill commented Jan 19, 2018

ewenmcneill commented Jan 19, 2018

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mithro commented Jan 19, 2018

mithro commented Jan 19, 2018

ewenmcneill commented Feb 8, 2018

rohitk-singh commented Feb 8, 2018

mithro commented Feb 9, 2018

WIP: Numato Elbert V2 support #12

WIP: Numato Elbert V2 support #12

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mithro commented Jan 18, 2018

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ewenmcneill commented Feb 8, 2018

rohitk-singh commented Feb 8, 2018

mithro commented Feb 9, 2018