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build(deps): bump third_party/litedram from 6c53996 to 401554f #210

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build(deps): bump third_party/litedram from 6c53996 to 401554f #210

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Bumps third_party/litedram from 6c53996 to 401554f.

Commits
  • 401554f Merge pull request #92 from gsomlo/gls-assert-width
  • 7356d3b frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native
  • 24203cf frontend/axi: add assertion on matching axi, native port data_width
  • d84e1b4 frontend/axi: add assert on axi.address_width and base_address
  • 1d037d2 frontend/axi: add base_address parameter to LiteDRAMAXI2Native
  • 5d1a984 core: add LiteDRAMCore (ControllerInjector from LiteX)
  • d647abd gen: fix with_wishbone
  • db97203 gen: use SoCCore with_wishbone parameter, do more replace in yml files before...
  • adf481f gen: disable peripherals that are not used when cpu_type is None
  • 2331919 gen: change CSR config names, switch to csr_expose/csr_align
  • Additional commits viewable in compare view

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@dependabot-preview dependabot-preview bot added the dependencies Pull requests that update a dependency file label Oct 30, 2019
@mithro mithro closed this Nov 5, 2019
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OK, I won't notify you again about this release, but will get in touch when a new version is available.

If you change your mind, just re-open this PR and I'll resolve any conflicts on it.

@dependabot-preview dependabot-preview bot deleted the dependabot/submodules/third_party/litedram-401554f branch November 5, 2019 01:00
piotr-binkowski pushed a commit to antmicro/litex-buildenv that referenced this pull request Nov 7, 2019
@mateusz-holenko
Updating submodules.
4583107 
 * edid-decode changed from 15df4ae to 42f5fa4
    * 42f5fa4 - edid-decode: add comment w.r.t. JOC <Hans Verkuil>
    * a479a24 - edid-decode: parse additional flags in the DD+ Short Audio Descriptor <Arnaud Vrac>

 * litedram changed from 67de3ce to 6c53996
    * 6c53996 - core/refresher: reduce refresh period by one cycle <Florent Kermarrec>
    * afb6d0a - core/refresher: reduce RefreshGenerator start delay by 1 cycle <Florent Kermarrec>
    * b543286 - test/test_refresh: add Refresher test <Florent Kermarrec>
    * 7daf355 - test/test_bist: remove vcd generation (only useful for debug) <Florent Kermarrec>
    * b4125fa - test/test_refresh: add RefreshTimer test <Florent Kermarrec>
    * 9584c2f - test: remove use of rand_wait, rename rand_level to random <Florent Kermarrec>
    * 0eef5d4 - test: add test_refresh with simple RefreshGenerator test <Florent Kermarrec>
    * 9348800 - test: rename test_timing_controllers to test_timing <Florent Kermarrec>
    * 8cf561d - test/test_timing_controllers: add simple tFAWController tests <Florent Kermarrec>
    * 3ae666d - test/test_timing_controllers: add simple tXXDController tests <Florent Kermarrec>
    * 394a49a - test: add test_timing_controllers with tXXDController test <Florent Kermarrec>
    * 6e3f769 - core: move timing controllers to common <Florent Kermarrec>
    * 54cdc7f - test: -x on tests <Florent Kermarrec>
    * 2ecb053 - frontend/ecc: move generic part of ECC to LiteX <Florent Kermarrec>
    * 8646b2e - test/test_adaption: use same DUT for up/down converter tests <Florent Kermarrec>
    * 9f9fed0 - test: merge test_downconverter/test_upconverter in a single test_adaptation file <Florent Kermarrec>
    * fc41751 - frontend/dma: simplify rsv_level expose <Florent Kermarrec>
    *   88835de - Merge pull request timvideos#86 from sergachev/master <enjoy-digital>
    |\
    | * f145287 - dma: expose reservation level in the reader <Ilia Sergachev>
    |/
    * f018c9e - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec>
    * 18dda2d - phy/s7ddrphy: increase _half_sys8x_taps CSR to 5 bits <Florent Kermarrec>
    * 690e4f8 - README: fix ECP5 frequency ratio <Florent Kermarrec>

 * liteeth changed from 2424e62 to ad187d3
    * ad187d3 - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec>
    * fd6d6c3 - mac: update imports <Florent Kermarrec>
    * a170acd - change MAC location (next to phy/core/frontend), keep import retro-compatibility <Florent Kermarrec>
    * 789dadd - liteeth/software: remove libwip/libuip examples. <Florent Kermarrec>

 * litepcie changed from de6cd01 to 71c9a3a
    * 71c9a3a - core/tlp: rewrite controller (simplify, always enable reordering) <Florent Kermarrec>
    * 619f5c5 - add CONTRIBUTORS file and copyright header to all files. <Florent Kermarrec>

 * litesata changed from 6fe4cce to db5d2f7
    * db5d2f7 - add CONTRIBUTORS and copyright header to all files. <Florent Kermarrec>

 * litescope changed from 2474ce9 to 9e3b9d8
    * 9e3b9d8 - add CONTRIBUTORS file and add copyright header to all files. <Florent Kermarrec>
    * 66956cb - Merge pull request timvideos#13 from keesj/arty_fast_scope <enjoy-digital>
    * 144bd06 - Add an example of sampling at 800Mhz using a serdes on arty. <kees.jongenburger>
    * 7f4dc39 - Add functionality to flatten values that are sampled using a serdes. <kees.jongenburger>

 * liteusb changed from 0a9110f to 7457a29
    * 7457a29 - README: deprecate, indicate new code location <Florent Kermarrec>

 * litex changed from 113f7f40 to e637aa65
    *   e637aa65 - Merge pull request timvideos#222 from antmicro/bump_vexriscv <enjoy-digital>
    |\
    | * 932475a2 - cpu/vexriscv: bump submodule <Mateusz Holenko>
    |/
    * bc7ab637 - bios/sdram: fix compilation warning <Florent Kermarrec>
    * a7895e49 - test/test_axi: remove use of rand_wait, rename rand_level to random <Florent Kermarrec>
    * 1cfb36e1 - soc_core: round memory regions size/length to next power of 2 (if not already a power of 2) <Florent Kermarrec>
    *   556d2c7c - Merge pull request timvideos#221 from antmicro/bump_vexriscv <enjoy-digital>
    |\
    | * 3e89c564 - cpu/vexriscv: bump submodule <Mateusz Holenko>
    |/
    * e673fce4 - bios/boot: fix default EMULATOR_RAM_BASE <Florent Kermarrec>
    * 0acacbaa - cores/clock: cleanup <Florent Kermarrec>
    * edf8aa8c - cores/clock: add initial iCE40 support <Florent Kermarrec>
    * 6d543358 - cores/spi_flash/add_clk_primitive: return if clk primitive is not needed <Florent Kermarrec>
    * 462d12ba - bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET <Florent Kermarrec>
    * fc12961e - soc_core: fix cpu_variant definition <Florent Kermarrec>
    * af61688d - bios/boot: fix booting rework <Florent Kermarrec>
    * 4b686dbd - soc_core: fix cpu_variant config (we don't want the extension) <Florent Kermarrec>
    *   7d9cf1d2 - Merge pull request timvideos#216 from antmicro/booting_vexriscv_linux <enjoy-digital>
    |\
    | * 8335f13f - bios/boot: rework netboot/flashboot for VexRiscv in linux variant <Mateusz Holenko>
    | * a19bdd0e - soc_core: generate extra string-based config defines <Mateusz Holenko>
    | * 005c0776 - soc_core: include information about cpu variant in csv and headers <Mateusz Holenko>
    * | 95cfd0b9 - cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now) <Florent Kermarrec>
    * | bfdcf4b2 - platforms/versa_ecp5: add spiflash pads <Florent Kermarrec>
    * | 41eb21b3 - soc_core: optimize mem_decoder <Florent Kermarrec>
    * | 0eff65bb - cores/up5ksram: optimize bus.adr decoding <Florent Kermarrec>
    * | bb99c468 - cores/up5kspram: simplify and add support for all width/depth configurations <Florent Kermarrec>
    * | eaf84b85 - cores/pwm: remove clock_domain support (better to use ClockDomainsRenamer), make csr optional <Florent Kermarrec>
    * | ea619e3a - cores/spi: rename add_control paramter to add_csr <Florent Kermarrec>
    * | ec411a6a - soc_core: add SoCMini class (SoCCore with no cpu, sram, uart, timer) for simple designs <Florent Kermarrec>
    * |   bca42f74 - Merge pull request timvideos#219 from flammit/fix-ecp5-pll <enjoy-digital>
    |\ \
    | |/
    |/|
    | * c6c74391 - soc: cores: fix name of EHXPLLL output clock in ECP5PLL <Francis Lam>
    |/
    * d3aaaf5e - cores/spi: fix/simplify loopback <Florent Kermarrec>
    * 59fda8da - README: update banner <Florent Kermarrec>
    * 769d15d4 - cores/spi: move CSR control/status to add_control method, add loopback capability and simple xfer loopback test <Florent Kermarrec>
    * ee8fec10 - soc/cores: add ECC (Error Correcting Code) <Florent Kermarrec>
    * 7dbddb3a - platforms/tinyfpga_bx: add serial extension <Florent Kermarrec>
    * 831a1916 - README: add a few links to papers/presentations/tutorials <Florent Kermarrec>
    *   95796c5b - Merge pull request timvideos#218 from railnova/zynq <enjoy-digital>
    |\
    | * dcf55ad4 - [fix] Slave interface HP0 clk name <chmousset>
    * |   08772fc0 - Merge pull request timvideos#217 from sergachev/master <enjoy-digital>
    |\ \
    | |/
    |/|
    | * dacec6aa - spi: change CSR to CSRStorage <Ilia Sergachev>
    |/
    * be280bed - soc_zynq: use zynq fabric reset as sys reset <Florent Kermarrec>
    * 220f4375 - soc_zynq: add missing axi hp0 clock <Florent Kermarrec>
    * 9c8c0371 - soc_zynq: move axi gp0 clock connection to add_gp0 method <Florent Kermarrec>
    * b0192e5f - soc_core: use fixed 16MB CSR address space <Florent Kermarrec>
    * 68a50317 - soc_sdram: limit main_ram to 512MB for now <Florent Kermarrec>
    * ccbf1418 - compiler-rt: update to new location, fixes timvideos#209 <Florent Kermarrec>
    * 21a5aaa4 - soc_core: declare csr address size when registering csr, fixes timvideos#212 <Florent Kermarrec>
    * 41b6fbde - soc_cores: fix typos <Florent Kermarrec>
    *   bff081a8 - Merge pull request timvideos#214 from gsomlo/gls-alignment-fixup <enjoy-digital>
    |\
    | * e42f33ed - soc_core: additional csr_alignment follow-up fixes <Gabriel L. Somlo>
    |/
    * f4770219 - soc_core: add csr_alignment to allow 64-bit alignment with 64-bit CPUs <Florent Kermarrec>
    * 927b7c13 - soc/integration: uniformize configuration constants declaration in SoCs (use self.config instead self.add_constant) <Florent Kermarrec>
    * 96f45bbd - software/libbase/id: update code (length is now fixed to 256) <Florent Kermarrec>
    * 282ae963 - cores: add simple PWM (Pulse Width Modulation) module <Florent Kermarrec>
    * 77e7f9b3 - core/spi: make cs_n optional (sometimes managed externally) <Florent Kermarrec>
    * e726ad80 - cores/spi_flash: add non-memory mapped S7SPIFlash modules based on SPIMaster (for design were we only want to re-program the bistream) <Florent Kermarrec>
    * 4c18c991 - cores: add ICAP core (tested with reconfiguration commands) <Florent Kermarrec>
    * 6b82f23c - cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency. <Florent Kermarrec>
    * ada70e8c - soc/cores/spi: remove too complicated and does not seem reliable in all cases. <Florent Kermarrec>
    * 7cd5c0f3 - cores: add bitbang class with minimal hardware for I2C/SPI software bit-banging <Florent Kermarrec>
    * d29b8419 - cores: remove nor_flash_16 (obsolete, most of the boards are now using SPI flash) <Florent Kermarrec>
    * 3f6bd266 - cores/gpio: remove Blinker <Florent Kermarrec>
    *   359b8fe4 - Merge pull request timvideos#210 from DurandA/master <Tim Ansell>
    |\
    | * 68eeba91 - Add verilog submodule from CPU cores to manifest <Arnaud Durand>
    |/
    * 4ee9c53f - csr: add assert to ensure CSR size < busword (thanks tweakoz) <Florent Kermarrec>
    * 0116b2b7 - soc_core: update default RocketChip mem_map <Florent Kermarrec>
    * 9d170b09 - soc_core: rearrange default mem_map <Florent Kermarrec>
    * 05b667bb - bios/main: fix #ifdefs for fw command <Florent Kermarrec>
    * 37687579 - libnet/tftp: fix compilation warning <Florent Kermarrec>
    * 9f3c8a9b - bios/main: fix spiflash compilation warnings <Florent Kermarrec>
    * 2da59b29 - soc_sdram: allow main_ram_size > 256MB (limitation no longer exists) <Florent Kermarrec>
    * b8d45af5 - targets: use new prefered way to add wishbone slave <Florent Kermarrec>
    * 7618b845 - soc_core: use new way to add wisbone slave (now prefered) <Florent Kermarrec>
    * 740629ba - soc_core: remove 256MB mem_map limitation <Florent Kermarrec>
    * b65968c3 - soc/core: remove #!/usr/bin/env python3 <Florent Kermarrec>
    *   f49d0fe6 - Merge pull request timvideos#206 from gsomlo/gls-tftp-spinner <enjoy-digital>
    |\
    | * 5a42dbf3 - BIOS: TFTP: ASCII spinner progress indicator (cosmetic) <Gabriel L. Somlo>
    |/
    *   d5177d72 - Merge pull request timvideos#204 from antmicro/write_to_flash <enjoy-digital>
    |\
    | * 2ee194b2 - bios: add fw (flash write) command <Mateusz Holenko>
    * | cef23690 - core/spi_flash: re-integrate bitbang write support <Florent Kermarrec>
    |/
    * 5cc4c334 - README: remove LiteUSB (deprecated) <Florent Kermarrec>
    * dc03b7fa - boards: community supported boards are now located at https://github.com/litex-hub/litex-boards <Florent Kermarrec>
    * 0af017e6 - liteeth: update mac imports (olds still works, but that's now the prefered way) <Florent Kermarrec>
    * ecf999b8 - soc/cores: add usb_fifo with FT245 USB FIFO PHY from LiteUSB, deprecate LiteUSB <Florent Kermarrec>
    * e667d5ae - README: update Intro <Florent Kermarrec>
    * 8f6e66ca - make sure #!/usr/bin/env python3 is before copyright header <Florent Kermarrec>
    * c7f36ab0 - test: add copyright header <Florent Kermarrec>
    * daa4307d - add CONTRIBUTORS file and add copyright header to all files <Florent Kermarrec>
    * 361f9d0d - bios/sdram: set init_done/error when DDRCTRL is present (litedram_gen) <Florent Kermarrec>
    * d8ac9362 - Convert top level comment to a docstring. <Tim 'mithro' Ansell>
    *   45632c66 - Merge pull request timvideos#202 from xobs/add-up5kspram <enjoy-digital>
    |\
    | * 7656f54d - soc: cores: add up5kspram module <William D. Jones>
    |/
    * 73dbffe8 - cores/frequency_meter: allow passing clk to be measured as a parameter <Florent Kermarrec>
    *   408d3f1f - Merge pull request timvideos#201 from gsomlo/gls-fix-initmem <enjoy-digital>
    |\
    | * ab827d21 - tools/litex_sim: fix default endianness for mem_init <Gabriel L. Somlo>
    |/
    *   f47b4902 - Merge pull request timvideos#200 from gsomlo/gls-rocket-variants <enjoy-digital>
    |\
    | * f75863fc - cpu/rocket: add "linux" (MMU) and "full" (MMU & FPU) variants <Gabriel L. Somlo>
    |/
    * c0df9e08 - cpu/rocket: update submodule <Florent Kermarrec>
    * 87118d50 - integration/soc_core: move cpu_variant checks/formating to cpu <Florent Kermarrec>
    * f6b67a6d - cpu/vexriscv: add "linux+no-dsp" variant <Florent Kermarrec>
    * 95b1b454 - cpu/vexriscv: update <Florent Kermarrec>
    * e46d287b - targets/ulx3s: use CAS latency of 3 to be compatible with production boards <Florent Kermarrec>

 * litex-renode changed from bd1d0a0 to a57aa47
    *   a57aa47 - Merge pull request timvideos#8 from antmicro/newest_litex_fixes <Tim Ansell>
    |\
    | * aebbe7f - Rework obtaining system clock frequency. <Mateusz Holenko>
    | * bd77b6c - Do not generate `csr` memory region. <Mateusz Holenko>
    |/
    * 0d3b303 - Merge pull request timvideos#7 from antmicro/support_more_peripherals <Tim Ansell>
    * 406eafb - Fix generation of SPI flash peripheral. <Mateusz Holenko>
    * ab22e8f - Change VexRiscv configuration. <Mateusz Holenko>
    * f799d28 - Generate `cpu` (CPU timer) peripheral. <Mateusz Holenko>
    * c2bea62 - Allow to set custom interrupts. <Mateusz Holenko>
    * 66a4add - Allow to override the peripheral name. <Mateusz Holenko>
    * 409b696 - Generate `cas` (Control And Status) peripheral. <Mateusz Holenko>
    * ae3bee6 - Generate `ethphy` peripheral. <Mateusz Holenko>

 * migen changed from 0.6.dev-283-g562c046 to 0.6.dev-289-g5585912
    * 5585912 - cdc: avoid race between data and request in BusSynchronizer <Sebastien Bourdeauducq>
    * f4979a2 - cdc: add BlindTransfer (from artiq.rtio.cdc) <Sebastien Bourdeauducq>
    * dd4ed5d - lattice/diamond: remove source/toolchain_path <Sebastien Bourdeauducq>
    * b0d9a18 - fix ISE build <Sebastien Bourdeauducq>
    * caab414 - build: remove tool version detection and sourcing of vendor script <Sebastien Bourdeauducq>
    * 5c5486b - xilinx: work around Vivado locale bug. Closes timvideos#183 <Sebastien Bourdeauducq>

Full submodule status
--
 42f5fa4ed99b669da4b4169a42eca7dbf5a293c7 edid-decode (remotes/origin/HEAD)
 1c21ee44a2b3936f62e4b43f2bcbf63ce9404691 flash_proxies (heads/master)
 6c53996a7042050def908882b36e92585b6ef138 litedram (remotes/origin/HEAD)
 ad187d35f2b967eb152adcc9f1998a914e5bb53a liteeth (heads/master)
 71c9a3a2eeaae8c4c44ffae14fb5417b94319206 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (heads/master)
 9e3b9d84ce6d0e895d0ac275df78ccbd0e0e0ab2 litescope (heads/master)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 98e145fba8c25394e9958bad67e2a457d145127e litevideo (heads/master)
 e637aa657b7c1163c7c21c4b972f4aa947406272 litex (remotes/origin/HEAD)
 a57aa47 litex-renode (remotes/origin/HEAD)
 558591288dd08302cb8830310ba6975757b58c72 migen (0.6.dev-289-g5585912)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this pull request Aug 4, 2020
@mateusz-holenko
Updating submodules.
4619b12 
 * litedram changed from f51052f to 47a0d5f
    * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec>
    *   02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital>
    |\
    | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar>
    | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar>
    | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar>
    | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar>
    | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar>
    | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar>
    | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar>
    | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar>
    | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar>
    | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar>
    | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar>
    | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar>
    | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar>
    | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar>
    *   71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital>
    |\
    | * 805a374 - Add support for TDQS mode. <Owen Kirby>
    |/
    * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec>

 * litescope changed from 15179cb to a80c964
    * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital>
    * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar>

 * litex changed from 7bf191ca to abc49964
    * abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec>
    * aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec>
    *   b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital>
    |\
    | * fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko>
    * 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec>
    * 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec>
    * 382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital>
    * f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar>
    * c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar>
    * 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar>

 * litex-boards changed from 2ce24df to ee28d7b
    * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec>
    *   623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital>
    |\
    | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos>
    |/
    * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec>
    * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec>
    * f058181 - README: fix typo. <Florent Kermarrec>
    * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec>
    * ecdc1ef - README: add missings . <Florent Kermarrec>
    * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec>
    * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec>
    * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec>
    * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec>
    * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec>
    * bb65692 - add LICENSE. <Florent Kermarrec>
    * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec>
    * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec>
    * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec>
    * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec>
    * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec>
    * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec>
    * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec>
    *   89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital>
    |\
    | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15>
    | * cf98393 - Add Misc <rob-ng15>
    * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec>
    * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec>
    |/
    * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec>
    * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec>
    * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec>
    * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec>

 * litex-devicetree changed from 4216376 to 81d837b

Full submodule status
--
 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 47a0d5fb9e552baa880afab57903a5966d1ee8a7 litedram (2020.04-88-g47a0d5f)
 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a)
 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04)
 0b6a4bb6e742fd4de38d7ca3674f91acc5985b35 litepcie (2020.04-56-g0b6a4bb)
 b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3)
 a80c9640757b61533f300f29628aec3b7316aca8 litescope (2020.04-4-ga80c964)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 abc49964ea6719866684b474e10167950b85854e litex (2020.04-574-gabc49964)
 ee28d7b5ec1e0bcbeacc342c82cf539a135fbeb3 litex-boards (2020.04-162-gee28d7b)
 81d837bc6897d083a6e1166269c186cd196e5cc7 litex-devicetree (heads/master)
 f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD)
 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)
 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380)
 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master)
 af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117)
 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489)
 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b)
 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this pull request Aug 5, 2020
@mateusz-holenko
Updating submodules.
bbe0121 
 * litedram changed from f51052f to 47a0d5f
    * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec>
    *   02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital>
    |\
    | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar>
    | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar>
    | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar>
    | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar>
    | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar>
    | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar>
    | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar>
    | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar>
    | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar>
    | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar>
    | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar>
    | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar>
    | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar>
    | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar>
    *   71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital>
    |\
    | * 805a374 - Add support for TDQS mode. <Owen Kirby>
    |/
    * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec>

 * litepcie changed from 0b6a4bb to 30456fc
    * 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec>

 * litescope changed from 15179cb to a80c964
    * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital>
    * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar>

 * litex changed from 9fc488bd to 00629c45
    * 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec>
    * ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec>
    * b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec>
    * b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec>
    * abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec>
    * aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec>
    *   b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital>
    |\
    | * fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko>
    * | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec>
    * | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec>
    * |   382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital>
    |\ \
    | |/
    |/|
    | * f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar>
    | * c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar>
    | * 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar>
    * | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec>
    * | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec>
    * | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec>
    * |   eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital>
    |\ \
    | * | 561331ed - debug: make CI print offending values <Gabriel Somlo>
    | * | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo>
    | * | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo>
    | * | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo>
    | * | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo>
    | * | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo>
    |/ /
    * | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec>
    * |   5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital>
    |\ \
    | * | 79ca4d96 - remove debugging <Pepijn de Vos>
    | * | f6e20700 - add openFPGAloader programmer <Pepijn de Vos>
    * | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec>
    * | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec>
    * | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec>
    * | |   c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital>
    |\ \ \
    | | |/
    | |/|
    | * | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar>
    * | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec>
    * | |   4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital>
    |\ \ \
    | * | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst>
    * | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec>
    * | | |   86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \
    | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990>
    | * | | |   e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec>
    * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec>
    | * | | |   789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 0696b409 - CHANGES: update. <Florent Kermarrec>
    * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec>
    * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec>
    * | | | |   9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \ \
    | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990>
    | |/ / / /
    | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990>
    |/ / / /
    * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec>
    * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec>
    |/ /
    * / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec>
    |/
    *   8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar>
    | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar>
    * |   ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross>
    |\ \
    | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross>
    | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross>
    * | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital>
    |\| |
    | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross>
    |/ /
    * | 83370399 - CHANGES: update. <Florent Kermarrec>
    * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec>
    |/
    * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec>
    * 8f92034d - CHANGES: update. <Florent Kermarrec>
    *   99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar>
    | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar>
    | * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar>
    | * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar>
    | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar>
    | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar>
    | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar>
    | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar>
    | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar>
    | * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar>
    | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar>
    | * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar>
    | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar>
    * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec>
    |/
    *   2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital>
    |\
    | * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski>
    * 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec>
    * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec>
    * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec>
    * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec>

 * litex-boards changed from 2ce24df to ee28d7b
    * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec>
    *   623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital>
    |\
    | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos>
    |/
    * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec>
    * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec>
    * f058181 - README: fix typo. <Florent Kermarrec>
    * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec>
    * ecdc1ef - README: add missings . <Florent Kermarrec>
    * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec>
    * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec>
    * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec>
    * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec>
    * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec>
    * bb65692 - add LICENSE. <Florent Kermarrec>
    * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec>
    * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec>
    * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec>
    * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec>
    * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec>
    * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec>
    * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec>
    *   89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital>
    |\
    | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15>
    | * cf98393 - Add Misc <rob-ng15>
    * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec>
    * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec>
    |/
    * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec>
    * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec>
    * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec>
    * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec>

Full submodule status
--
 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 47a0d5fb9e552baa880afab57903a5966d1ee8a7 litedram (2020.04-88-g47a0d5f)
 792013a1756ea50608726ee86989ec38cfc35a8b liteeth (2020.04-21-g792013a)
 6fdd02058fba29008c90b162e0ef707dce15ebeb liteiclink (2020.04)
 30456fcb0697ef6c9252b9f2c0b2edf0c45ea353 litepcie (2020.04-57-g30456fc)
 b36d3a33fbbfcffdb77a7a9e05bc8121387858d3 litesata (2020.04-1-gb36d3a3)
 a80c9640757b61533f300f29628aec3b7316aca8 litescope (2020.04-4-ga80c964)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 00629c45b0ecb44149893439d040d4b4267ba4ea litex (2020.04-578-g00629c45)
 ee28d7b5ec1e0bcbeacc342c82cf539a135fbeb3 litex-boards (2020.04-162-gee28d7b)
 f1792587a9b50732578e0166cb5d1d83b126cfa6 litex-renode (remotes/origin/HEAD)
 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
 8f5a253b22cd4ebcd56304a3662f4c70e3b34ed5 nmigen (v0.1-69-g8f5a253)
 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.04-5-g4833380)
 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (heads/master)
 af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.04-5-gaf56117)
 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.04-5-g8897489)
 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.04-7-g654057b)
 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.04-5-g7cfcaed2)
mateusz-holenko added a commit to antmicro/litex-buildenv that referenced this pull request Aug 25, 2020
@mateusz-holenko
Updating submodules.
ddc5f3a 
 * litedram changed from f51052f to 2020.08-3-g5c69da5
    * 5c69da5 - bench: add initial kcu105 bench target. <Florent Kermarrec>
    * 9995c0f - bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. <Florent Kermarrec>
    * ac825e5 - add SPDX License identifier to header and specify file is part of LiteDRAM. <Florent Kermarrec>
    * 198bcba - test/reference: update. <Florent Kermarrec>
    * e3b86fe - getting started: update. <Florent Kermarrec>
    * a0a886e - litedram/init: export xdr ratio and databits. <Florent Kermarrec>
    * 94241d0 - bench: use new platform.request_all on LedChaser. <Florent Kermarrec>
    * 7420597 - bench: add genesys2 bench. <Florent Kermarrec>
    * 37fb44f - add bench directory with a first bench on arty board. <Florent Kermarrec>
    * 4e62d28 - examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). <Florent Kermarrec>
    * 07bf34d - frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. <Florent Kermarrec>
    * 9c5ce52 - common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. <Florent Kermarrec>
    * 06f7192 - frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. <Florent Kermarrec>
    * a3dfc1d - frontend/adapter: minor cleanups. <Florent Kermarrec>
    * deac4c8 - frontend/adapter: simplify LiteDRAMNativePortDownConverter. <Florent Kermarrec>
    * ce4e7f9 - frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. <Florent Kermarrec>
    * 16fd46b - frontend: rename adaptation to adapter. <Florent Kermarrec>
    * 4970c8a - frontend/wishbone: simplify/review and get FSM back (ease comprehension). <Florent Kermarrec>
    * 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec>
    *   02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital>
    |\
    | * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar>
    | * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar>
    | * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar>
    | * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar>
    | * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar>
    | * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar>
    | * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar>
    | * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar>
    | * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar>
    | * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar>
    | * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar>
    | * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar>
    | * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar>
    | * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar>
    *   71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital>
    |\
    | * 805a374 - Add support for TDQS mode. <Owen Kirby>
    |/
    * c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec>

 * liteeth changed from 792013a to 54acf9f
    * 54acf9f - phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). <Florent Kermarrec>
    * 64b85e6 - add SPDX License identifier to header and specify file is part or LiteEth. <Florent Kermarrec>
    * f275af8 - liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. <Florent Kermarrec>
    * 0705b35 - Merge pull request timvideos#46 from Xiretza/gen-py-wishbone <enjoy-digital>
    * 6a9a513 - Update gen.py to work with latest LiteX in wishbone mode <Xiretza>

 * liteiclink changed from 6fdd020 to 2020.08-1-gefd200f
    * efd200f - add SPDX License identifier to header and specify file is part of LiteICLink. <Florent Kermarrec>
    * 60b1994 - getting started: update. <Florent Kermarrec>

 * litepcie changed from 0b6a4bb to 2020.08-1-g0718fd1
    * 0718fd1 - add SPDX License identifier to header and specify file is part of LitePCIe. <Florent Kermarrec>
    * 29d4963 - getting started: update. <Florent Kermarrec>
    * 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec>

 * litesata changed from b36d3a3 to 2020.08-1-gba006a7
    * ba006a7 - add SPDX License identifier to header and specify file is part of LiteSATA. <Florent Kermarrec>
    * 2e4591c - getting started: update. <Florent Kermarrec>

 * litescope changed from 15179cb to 2020.08-2-g02b543e
    * 02b543e - litescope_cli: add capture subsampling support. <Florent Kermarrec>
    * 2739d5a - add SPDX License identifier to header and specify file is part of LiteScope. <Florent Kermarrec>
    * ec7bd6b - getting started: update. <Florent Kermarrec>
    *   7d22774 - Merge pull request timvideos#27 from cklarhorst/fix-storage-wrong-clock-domain <enjoy-digital>
    |\
    | * ad4e46c - Fix: 2 signals in the storage class belong to the wrong clock domain <Christian Klarhorst>
    |/
    *   2ad73a0 - Merge pull request timvideos#25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain <enjoy-digital>
    |\
    | * 16e6555 - Fix: A WaitTimer belongs to the wrong clock domain (trigger flush) <Christian Klarhorst>
    |/
    * 0066866 - travis: install riscv toolchain for example. <Florent Kermarrec>
    * 6a322ed - test/test_examples: update. <Florent Kermarrec>
    * bc6c5e3 - examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer. <Florent Kermarrec>
    * 0182377 - examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script. <Florent Kermarrec>
    * a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital>
    * 8b0274d - examples: add a more general script for testing <Jędrzej Boczar>

 * litex changed from 9fc488bd to 3897acb9
    * 3897acb9 - lattice/nx: update copyrights. <Florent Kermarrec>
    * 4364043b - integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). <Florent Kermarrec>
    * 885c339d - soc/cores: add initial NX-LRAM support. <Piense>
    * cf13833e - cores/clock: add initial NX-OSCA support. <Piense>
    * e441bd60 - build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). <Piense>
    *   8a44464a - Merge pull request timvideos#640 from antmicro/mor1kx_dt <enjoy-digital>
    |\
    | * 4dab1eb0 - litex_json2dts: Add support for mor1kx <Mateusz Holenko>
    * | 4f1c32ab - targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. <Florent Kermarrec>
    * | d16051ff - boards/ulx3s: keep up to date with litex-boards. <Florent Kermarrec>
    * | d826c606 - soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. <Florent Kermarrec>
    * | 9e37b16e - soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. <Florent Kermarrec>
    |/
    *   42d8fc22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   ee0e2402 - Merge pull request timvideos#631 from gsomlo/gls-abc9-fixup <enjoy-digital>
    | |\
    | | * c4710b37 - build/lattice/trellis: make "-abc9" an optional argument <Gabriel Somlo>
    * | | 77ae2433 - test: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    * | | b8371ef4 - tools: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    * | | 93d906f9 - soc: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
    * | | e52ffd2d - gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. <Florent Kermarrec>
    * | | 70610b23 - build: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
    * | | 6ee882d1 - platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
    |/ /
    * | 9950e756 - build/io: fix InferedSDRIO (thanks @mtdudek). <Florent Kermarrec>
    * |   bae871a8 - Merge pull request timvideos#632 from gsomlo/gls-sdcard-refactor <enjoy-digital>
    |\ \
    | * | e0b2b815 - liblitesdcard/sdcard: read sdcard response only when needed <Gabriel Somlo>
    | * | a47b2de5 - sdcard: refactor command functions <Gabriel Somlo>
    | * | bfd6b3c3 - liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) <Gabriel Somlo>
    | * | 37ebcd3b - factor out busy_wait_us() <Gabriel Somlo>
    | |/
    * |   3206dba9 - Merge pull request timvideos#636 from Xiretza/minerva-cli-filetype <enjoy-digital>
    |\ \
    | * | e3bb3a94 - Fix call to generation of minerva output file <Xiretza>
    | |/
    * |   8bc5dd7c - Merge pull request timvideos#635 from Xiretza/collections-abc-deprecation <enjoy-digital>
    |\ \
    | * | fcc7058b - Fix DeprecationWarning for collections.abc <Xiretza>
    | |/
    * |   79844362 - Merge pull request timvideos#634 from betrusted-io/spi_opi_timing_only <enjoy-digital>
    |\ \
    | |/
    |/|
    | * d783e86f - add a pipe register to relax an async_default timing path <bunnie>
    * | 35929c0f - soc/integration/csr_bridge: use registered version only when SDRAM is present. <Florent Kermarrec>
    * | e4f5dd98 - interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. <Florent Kermarrec>
    * | b344196a - build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). <Florent Kermarrec>
    * | f730f1d7 - cores/cpu/vexriscv_smp fix argument parsing <Dolu1990>
    * | 0e480dd6 - bios/main/sdram: fix speed reporting (Mbps/pin not MHz). <Florent Kermarrec>
    * |   bb7f3343 - Merge pull request timvideos#627 from gsomlo/gls-dma-addr-64 <enjoy-digital>
    |\ \
    | * | ba34c852 - cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address <Gabriel Somlo>
    |/ /
    * | 4cf28a01 - software/bios: display SDRAM databits and freq. <Florent Kermarrec>
    * | 6f69679d - cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. <Florent Kermarrec>
    * | b3531cd2 - cores/cpu: add external cpu_type. <Florent Kermarrec>
    * | b9d3aab5 - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
    * | 14c91664 - build/generic_platform: add request_all method. <Florent Kermarrec>
    * | 57335b99 - cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. <Florent Kermarrec>
    * |   4867f2b3 - Merge pull request timvideos#624 from trabucayre/emio_zynq <enjoy-digital>
    |\ \
    | * | 87c26a30 - soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode <Gwenhael Goavec-Merou>
    * | | 48d63f23 - build/generic_plaform: add loose parameter to return None when not available/existing. <Florent Kermarrec>
    * | |   81df7b70 - Merge pull request timvideos#625 from scanakci/blackparrot_litex <enjoy-digital>
    |\ \ \
    | * | | 2457859b - update BlackParrot transducer <sadullah>
    | * | | d2dabcef - Blackparrot human name update <sadullah>
    | |/ /
    * / / 188e6f57 - integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. <Florent Kermarrec>
    |/ /
    * |   d5062d1f - Merge pull request timvideos#623 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \
    | * | 07a8e696 - cpu/vexriscv_smp Add --with-coherent-dma <Dolu1990>
    |/ /
    * | 9a4c5aa1 - integration/soc/add_sdram: update rules to connect main bus to dram. <Florent Kermarrec>
    * | a1644510 - cpu/vexriscv_smp: fix args_read. <Florent Kermarrec>
    * | 896b68cd - cpu/vexriscv_smp: cleanup, fix coherent_dma connection. <Florent Kermarrec>
    * |   342f359e - Merge pull request timvideos#622 from antmicro/fix_connectors <enjoy-digital>
    |\ \
    | * | de9ea19c - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
    * | | 3b293612 - soc/interconnect/axi: minor cleanups. <Florent Kermarrec>
    * | | 303d6cca - interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. <Florent Kermarrec>
    * | | 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec>
    * | | ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec>
    * | | b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec>
    * | | b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec>
    | |/
    |/|
    * | abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec>
    * | aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec>
    * |   b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital>
    |\ \
    | * | fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko>
    * | | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec>
    * | | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec>
    * | |   382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar>
    | * | c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar>
    | * | 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar>
    * | | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec>
    * | | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec>
    * | | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec>
    * | |   eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital>
    |\ \ \
    | * | | 561331ed - debug: make CI print offending values <Gabriel Somlo>
    | * | | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo>
    | * | | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo>
    | * | | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo>
    | * | | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo>
    | * | | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo>
    |/ / /
    * | | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec>
    * | |   5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital>
    |\ \ \
    | * | | 79ca4d96 - remove debugging <Pepijn de Vos>
    | * | | f6e20700 - add openFPGAloader programmer <Pepijn de Vos>
    * | | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec>
    * | | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec>
    * | | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec>
    * | | |   c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital>
    |\ \ \ \
    | | |/ /
    | |/| |
    | * | | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar>
    * | | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec>
    * | | |   4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital>
    |\ \ \ \
    | * | | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst>
    * | | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec>
    | |_|_|/
    |/| | |
    * | | |   86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \
    | * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990>
    | * | | |   e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec>
    * | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec>
    | * | | |   789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990>
    | |\ \ \ \
    | |/ / / /
    |/| | | |
    * | | | | 0696b409 - CHANGES: update. <Florent Kermarrec>
    * | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec>
    * | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec>
    * | | | |   9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital>
    |\ \ \ \ \
    | | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990>
    | |/ / / /
    | * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990>
    |/ / / /
    * | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec>
    * | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec>
    | |_|/
    |/| |
    * | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec>
    |/ /
    * / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec>
    |/
    *   8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar>
    | * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar>
    * |   ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross>
    |\ \
    | * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross>
    | * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross>
    * | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital>
    |\| |
    | * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross>
    |/ /
    * | 83370399 - CHANGES: update. <Florent Kermarrec>
    * | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec>
    |/
    * 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec>
    * 8f92034d - CHANGES: update. <Florent Kermarrec>
    *   99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital>
    |\
    | * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar>
    | * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar>
    | * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar>
    | * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar>
    | * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar>
    | * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar>
    | * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar>
    | * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar>
    | * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar>
    | * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar>
    | * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar>
    | * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar>
    | * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar>
    * | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec>
    |/
    *   2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital>
    |\
    | * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski>
    * 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec>
    * 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec>
    * 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec>
    * 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec>

 * litex-boards changed from 2ce24df to 2020.08-9-g63b65e2
    * 63b65e2 - crosslink_nx_evn: update copyrights. <Florent Kermarrec>
    * 153326f - targets/icebreaker: update flash. <Florent Kermarrec>
    * 795e34a - add initial Crosslink-NX support. <Piense>
    * 84c19a6 - targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. <Florent Kermarrec>
    * 70594a5 - ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. <Florent Kermarrec>
    * 1781be1 - general: add SPDX License identifier to header and specify files are part of LiteX-Boards. <Florent Kermarrec>
    * 83d8b8d - platforms/acorn_cle_215: integrated sdcard ios as extension. <Florent Kermarrec>
    *   d365836 - Merge pull request timvideos#100 from connorwk/master <enjoy-digital>
    |\
    | * f328909 - Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. <connorwk>
    |/
    * 45bb329 - targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. <Florent Kermarrec>
    * b6a1ad5 - targets/orangecrab: add simple CRG when built without DDR3. <Florent Kermarrec>
    * 869cead - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
    *   8583c44 - Merge pull request timvideos#98 from antmicro/arty_pmod_configuration <enjoy-digital>
    |\
    | * d2cd6d4 - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
    |/
    * ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec>
    *   623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital>
    |\
    | * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos>
    |/
    * 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec>
    * 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec>
    * f058181 - README: fix typo. <Florent Kermarrec>
    * 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec>
    * ecdc1ef - README: add missings . <Florent Kermarrec>
    * 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec>
    * 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec>
    * eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec>
    * 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec>
    * bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec>
    * bb65692 - add LICENSE. <Florent Kermarrec>
    * e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec>
    * 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec>
    * 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec>
    * d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec>
    * 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec>
    * 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec>
    * b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec>
    *   89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital>
    |\
    | * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15>
    | * cf98393 - Add Misc <rob-ng15>
    * | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec>
    * | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec>
    |/
    * e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec>
    * 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec>
    * 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec>
    * 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec>

 * litex-renode changed from f179258 to 3d01f40
    * 3d01f40 - Merge pull request timvideos#29 from antmicro/i2c_generation <Mateusz Hołenko>
    * ed34c42 - generate-renode-scripts: Add I2C support <Mateusz Holenko>
    * a431211 - generate-zephyr-dts: Add I2C support <Mateusz Holenko>
    * 9f4f0fb - [FIX] Fix config generation <Mateusz Holenko>

 * nmigen changed from 8f5a253 to 1ad6e32
    * 1ad6e32 - Clifford -> Claire <Sebastien Bourdeauducq>
    * 40f7f12 - Add option to specify solver in nmigen.test.utils <Donald Sebastian Leung>

Full submodule status
--
 2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
 3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
 5c69da5d6db245dedab479509c0eaa8c1c80027c litedram (2020.08-3-g5c69da5)
 54acf9fd76c226d7760294ffde86418e52e0951b liteeth (2020.04-26-g54acf9f)
 efd200fa9e625144131a310fc09fd1fecf1682e6 liteiclink (2020.08-1-gefd200f)
 0718fd135fc30e0a3598eaf66ce2fcb54b62193c litepcie (2020.08-1-g0718fd1)
 ba006a78c12e25354dafb021510c043dbe070614 litesata (2020.08-1-gba006a7)
 02b543e5ba24c025212515f6e32f542629d823e8 litescope (2020.08-2-g02b543e)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
 41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
 3897acb9e4b91ad58abbcea8e3cff6e44223bd02 litex (2020.04-639-g3897acb9)
 63b65e278c279a9cf8c4da31db8f7e845edba394 litex-boards (2020.08-9-g63b65e2)
 3d01f408539b4641f9d2b42ebd8237436e49d16b litex-renode (remotes/origin/HEAD)
 7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
 1ad6e3207f02e913407867dddddb8f50fad0ced4 nmigen (v0.1-71-g1ad6e32)
 48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.08)
 4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (2020.08)
 af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.08)
 88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.08)
 654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.08)
 7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.08)
 da4c8c72eeb22894369b3936abb73f828f222b8e valentyusb (v0.3.3-195-gda4c8c7)
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