build(deps): bump third_party/liteeth from 54acf9f to 7448170
#610
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Bumps [third_party/liteeth](https://github.com/enjoy-digital/liteeth) from `54acf9f` to `7448170`. - [Release notes](https://github.com/enjoy-digital/liteeth/releases) - [Commits](enjoy-digital/liteeth@54acf9f...7448170) Signed-off-by: dependabot-preview[bot] <[email protected]>
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Jan 3, 2021
* litedram changed from f51052f to 2020.08-3-g5c69da5
* 5c69da5 - bench: add initial kcu105 bench target. <Florent Kermarrec>
* 9995c0f - bench: switch integrated_rom to "rw" mode and reload it over Etherbone at startup. <Florent Kermarrec>
* ac825e5 - add SPDX License identifier to header and specify file is part of LiteDRAM. <Florent Kermarrec>
* 198bcba - test/reference: update. <Florent Kermarrec>
* e3b86fe - getting started: update. <Florent Kermarrec>
* a0a886e - litedram/init: export xdr ratio and databits. <Florent Kermarrec>
* 94241d0 - bench: use new platform.request_all on LedChaser. <Florent Kermarrec>
* 7420597 - bench: add genesys2 bench. <Florent Kermarrec>
* 37fb44f - add bench directory with a first bench on arty board. <Florent Kermarrec>
* 4e62d28 - examples/.yml: set cmd_latency to 1 on Kintex7/Ultrascale (values valided in LiteX-Boards). <Florent Kermarrec>
* 07bf34d - frontend/wishbone: revert non-FSM version, the FSM one does not seem to cover all cases. <Florent Kermarrec>
* 9c5ce52 - common: add connect method to LiteDRAMNativePort and use it in adapter for identify converter. <Florent Kermarrec>
* 06f7192 - frontend/adapter/LiteDRAMNativePortConverter: simplify using ratio. <Florent Kermarrec>
* a3dfc1d - frontend/adapter: minor cleanups. <Florent Kermarrec>
* deac4c8 - frontend/adapter: simplify LiteDRAMNativePortDownConverter. <Florent Kermarrec>
* ce4e7f9 - frontend/adapter: simplify LiteDRAMNativePortCDC using stream.ClockDomainCrossing. <Florent Kermarrec>
* 16fd46b - frontend: rename adaptation to adapter. <Florent Kermarrec>
* 4970c8a - frontend/wishbone: simplify/review and get FSM back (ease comprehension). <Florent Kermarrec>
* 47a0d5f - litedram_gen/LiteDRAMUSDDRPHYCRG: remove AsyncResetSynchronizer on sys/sys4x (reset handled by USIDELAYCTRL). <Florent Kermarrec>
* 02e67ec - Merge pull request timvideos#192 from antmicro/jboc/port-adaptation <enjoy-digital>
|\
| * 22bd01c - frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter <Jędrzej Boczar>
| * b0bde29 - frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ <Jędrzej Boczar>
| * 79314f9 - frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 <Jędrzej Boczar>
| * 000a352 - frontend/adaptation: delay sending write commands to prevent data loss during up-conversion <Jędrzej Boczar>
| * 84fb7d3 - frontend/adaptation: refactor up-converter logic to use FSM for clarity <Jędrzej Boczar>
| * efe9a44 - frontend/adaptation: clean up LiteDRAMNativePortUpConverter code <Jędrzej Boczar>
| * 2f35e97 - frontend/adaptation: fix error when read follows write to the same address <Jędrzej Boczar>
| * 1587ee3 - frontend/adaptation: use port.cmd.last instead of port.flush in up-converter <Jędrzej Boczar>
| * 35fa91c - test/crossbar: up-conversion with mode="both" should be working now <Jędrzej Boczar>
| * 9b90a56 - frontend/adaptation: combine read/write port up-converters and extend tests <Jędrzej Boczar>
| * 762cd6d - test/adaptation: add port converter tests with mode="both" <Jędrzej Boczar>
| * 7a0f7a7 - test/common: fix error in test data <Jędrzej Boczar>
| * 1cc9656 - test/crossbar: improve NativePortDriver to use separate generatos on data paths <Jędrzej Boczar>
| * 025e280 - test/crossbar: fix test that was not being run <Jędrzej Boczar>
* 71b991e - Merge pull request timvideos#210 from oskirby/ddr3-tdqs-mode <enjoy-digital>
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| * 805a374 - Add support for TDQS mode. <Owen Kirby>
|/
* c01e868 - phy/gensdrphy/HalfRateGENSDRPHY: review/simplify and reduce read_latency by 1. <Florent Kermarrec>
* liteeth changed from 792013a to 54acf9f
* 54acf9f - phy/pcs_1000basex: keep up to date with MiSoC (adds SGMII and 10/100Mbps support). <Florent Kermarrec>
* 64b85e6 - add SPDX License identifier to header and specify file is part or LiteEth. <Florent Kermarrec>
* f275af8 - liteeth_gen: get Wishbone Platform's IOs with Interface.get_ios. <Florent Kermarrec>
* 0705b35 - Merge pull request timvideos#46 from Xiretza/gen-py-wishbone <enjoy-digital>
* 6a9a513 - Update gen.py to work with latest LiteX in wishbone mode <Xiretza>
* liteiclink changed from 6fdd020 to 2020.08-1-gefd200f
* efd200f - add SPDX License identifier to header and specify file is part of LiteICLink. <Florent Kermarrec>
* 60b1994 - getting started: update. <Florent Kermarrec>
* litepcie changed from 0b6a4bb to 2020.08-1-g0718fd1
* 0718fd1 - add SPDX License identifier to header and specify file is part of LitePCIe. <Florent Kermarrec>
* 29d4963 - getting started: update. <Florent Kermarrec>
* 30456fc - litepcie_gen: add csr_ordering support. <Florent Kermarrec>
* litesata changed from b36d3a3 to 2020.08-1-gba006a7
* ba006a7 - add SPDX License identifier to header and specify file is part of LiteSATA. <Florent Kermarrec>
* 2e4591c - getting started: update. <Florent Kermarrec>
* litescope changed from 15179cb to 2020.08-2-g02b543e
* 02b543e - litescope_cli: add capture subsampling support. <Florent Kermarrec>
* 2739d5a - add SPDX License identifier to header and specify file is part of LiteScope. <Florent Kermarrec>
* ec7bd6b - getting started: update. <Florent Kermarrec>
* 7d22774 - Merge pull request timvideos#27 from cklarhorst/fix-storage-wrong-clock-domain <enjoy-digital>
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| * ad4e46c - Fix: 2 signals in the storage class belong to the wrong clock domain <Christian Klarhorst>
|/
* 2ad73a0 - Merge pull request timvideos#25 from cklarhorst/fix-trigger-flush-timer-wrong-clock-domain <enjoy-digital>
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| * 16e6555 - Fix: A WaitTimer belongs to the wrong clock domain (trigger flush) <Christian Klarhorst>
|/
* 0066866 - travis: install riscv toolchain for example. <Florent Kermarrec>
* 6a322ed - test/test_examples: update. <Florent Kermarrec>
* bc6c5e3 - examples: add mininal example on Arty with Etherbone and ibus/counter on analyzer. <Florent Kermarrec>
* 0182377 - examples: remove obsolete examples rename litescope_test to litescope_cli and add it as console script. <Florent Kermarrec>
* a80c964 - Merge pull request timvideos#22 from antmicro/jboc/test-script <enjoy-digital>
* 8b0274d - examples: add a more general script for testing <Jędrzej Boczar>
* litex changed from 9fc488bd to 3897acb9
* 3897acb9 - lattice/nx: update copyrights. <Florent Kermarrec>
* 4364043b - integration/soc: expose integrated_rom_mode to allow ROM to be writable (useful for BIOS/ROM development where content is reloaded over UARTBone/Etherbone). <Florent Kermarrec>
* 885c339d - soc/cores: add initial NX-LRAM support. <Piense>
* cf13833e - cores/clock: add initial NX-OSCA support. <Piense>
* e441bd60 - build/lattice: add initial Radiant support for NX FPGA family (Crosslink-NX/Certus-NX). <Piense>
* 8a44464a - Merge pull request timvideos#640 from antmicro/mor1kx_dt <enjoy-digital>
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| * 4dab1eb0 - litex_json2dts: Add support for mor1kx <Mateusz Holenko>
* | 4f1c32ab - targets/de0nano: set sys2x_ps to 180° for sdram_rate=1:2. <Florent Kermarrec>
* | d16051ff - boards/ulx3s: keep up to date with litex-boards. <Florent Kermarrec>
* | d826c606 - soc/cores/clock/ECP5PLL: specificy CLKOS3_F/CPHASE and -1 on cphase to match Clarity Designer values. <Florent Kermarrec>
* | 9e37b16e - soc/interconnect/axi/AXILite2CSR: add register parameter for genericity. <Florent Kermarrec>
|/
* 42d8fc22 - Merge branch 'master' of https://github.com/enjoy-digital/litex <Florent Kermarrec>
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| * ee0e2402 - Merge pull request timvideos#631 from gsomlo/gls-abc9-fixup <enjoy-digital>
| |\
| | * c4710b37 - build/lattice/trellis: make "-abc9" an optional argument <Gabriel Somlo>
* | | 77ae2433 - test: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
* | | b8371ef4 - tools: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
* | | 93d906f9 - soc: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
* | | e52ffd2d - gen: add specify SPDX License identifier and specify file is part of Migen and has been modified/adapted for LiteX. <Florent Kermarrec>
* | | 70610b23 - build: add SPDX License identifier and specify file is part of LiteX. <Florent Kermarrec>
* | | 6ee882d1 - platforms/targets: add SPDX License identifier to header and specify file is part of LiteX. <Florent Kermarrec>
|/ /
* | 9950e756 - build/io: fix InferedSDRIO (thanks @mtdudek). <Florent Kermarrec>
* | bae871a8 - Merge pull request timvideos#632 from gsomlo/gls-sdcard-refactor <enjoy-digital>
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| * | e0b2b815 - liblitesdcard/sdcard: read sdcard response only when needed <Gabriel Somlo>
| * | a47b2de5 - sdcard: refactor command functions <Gabriel Somlo>
| * | bfd6b3c3 - liblitesdcard/sdcard: cosmetic fixes (indentation, #ifdef, etc.) <Gabriel Somlo>
| * | 37ebcd3b - factor out busy_wait_us() <Gabriel Somlo>
| |/
* | 3206dba9 - Merge pull request timvideos#636 from Xiretza/minerva-cli-filetype <enjoy-digital>
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| * | e3bb3a94 - Fix call to generation of minerva output file <Xiretza>
| |/
* | 8bc5dd7c - Merge pull request timvideos#635 from Xiretza/collections-abc-deprecation <enjoy-digital>
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| * | fcc7058b - Fix DeprecationWarning for collections.abc <Xiretza>
| |/
* | 79844362 - Merge pull request timvideos#634 from betrusted-io/spi_opi_timing_only <enjoy-digital>
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| |/
|/|
| * d783e86f - add a pipe register to relax an async_default timing path <bunnie>
* | 35929c0f - soc/integration/csr_bridge: use registered version only when SDRAM is present. <Florent Kermarrec>
* | e4f5dd98 - interconnect/wishbone/Wishbone2CSR: add registered version and use it as default. <Florent Kermarrec>
* | b344196a - build/lattice/diamond: use diamondc instead of pnmainc (avoid having to set environment variables). <Florent Kermarrec>
* | f730f1d7 - cores/cpu/vexriscv_smp fix argument parsing <Dolu1990>
* | 0e480dd6 - bios/main/sdram: fix speed reporting (Mbps/pin not MHz). <Florent Kermarrec>
* | bb7f3343 - Merge pull request timvideos#627 from gsomlo/gls-dma-addr-64 <enjoy-digital>
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| * | ba34c852 - cores/dma, liblitesdcard/sdcard: use 64 bits for dma base address <Gabriel Somlo>
|/ /
* | 4cf28a01 - software/bios: display SDRAM databits and freq. <Florent Kermarrec>
* | 6f69679d - cpu/vexriscv_smp: more coherent_dma to __init__ instead of add_memory_buses. <Florent Kermarrec>
* | b3531cd2 - cores/cpu: add external cpu_type. <Florent Kermarrec>
* | b9d3aab5 - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
* | 14c91664 - build/generic_platform: add request_all method. <Florent Kermarrec>
* | 57335b99 - cores/cpu/zynq7000: simplify using new loose parameter of Platform.request. <Florent Kermarrec>
* | 4867f2b3 - Merge pull request timvideos#624 from trabucayre/emio_zynq <enjoy-digital>
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| * | 87c26a30 - soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio, sdio_cd and sdio_wp only when configured in EMIO mode <Gwenhael Goavec-Merou>
* | | 48d63f23 - build/generic_plaform: add loose parameter to return None when not available/existing. <Florent Kermarrec>
* | | 81df7b70 - Merge pull request timvideos#625 from scanakci/blackparrot_litex <enjoy-digital>
|\ \ \
| * | | 2457859b - update BlackParrot transducer <sadullah>
| * | | d2dabcef - Blackparrot human name update <sadullah>
| |/ /
* / / 188e6f57 - integration/soc/add_etherbone: pass phy to ethcore not self.ethphy. <Florent Kermarrec>
|/ /
* | d5062d1f - Merge pull request timvideos#623 from Dolu1990/vexriscv_smp <enjoy-digital>
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| * | 07a8e696 - cpu/vexriscv_smp Add --with-coherent-dma <Dolu1990>
|/ /
* | 9a4c5aa1 - integration/soc/add_sdram: update rules to connect main bus to dram. <Florent Kermarrec>
* | a1644510 - cpu/vexriscv_smp: fix args_read. <Florent Kermarrec>
* | 896b68cd - cpu/vexriscv_smp: cleanup, fix coherent_dma connection. <Florent Kermarrec>
* | 342f359e - Merge pull request timvideos#622 from antmicro/fix_connectors <enjoy-digital>
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| * | de9ea19c - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
* | | 3b293612 - soc/interconnect/axi: minor cleanups. <Florent Kermarrec>
* | | 303d6cca - interconnect/stream: set default AsyncFIFO depth to None and add depth parameter to ClockDomainCrossing. <Florent Kermarrec>
* | | 00629c45 - interconnect/csr: add CSR registers ordering support. <Florent Kermarrec>
* | | ee7a7f46 - soc/interconnect/csr: improve ident. <Florent Kermarrec>
* | | b1008b01 - integration/soc: add expection on decoder when full address space is mapped. <Florent Kermarrec>
* | | b831dc8c - wishbone: revert default adr_width to 30. <Florent Kermarrec>
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|/|
* | abc49964 - tools/litex_json2dts: add missing copyrights. <Florent Kermarrec>
* | aed0dcee - setup: add litex_json2dts to console_scripts. <Florent Kermarrec>
* | b64209b3 - Merge pull request timvideos#620 from antmicro/add_litex_json2dts <enjoy-digital>
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| * | fafa844a - json2dts: Add Linux DT generation script <Mateusz Holenko>
* | | 0ca99b79 - build/sim/config: add default_clk/default_clk_freq parameters for retro-compatibility with previous API. <Florent Kermarrec>
* | | 696ea468 - build/sim: use json_object_get_int64 instead of json_object_get_uint64. <Florent Kermarrec>
* | | 382c1a3a - Merge pull request timvideos#619 from antmicro/jboc/sim-clocker <enjoy-digital>
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| |/ /
|/| |
| * | f778ff09 - build/sim: improve timebase calculation (strict checks) and update modules <Jędrzej Boczar>
| * | c1ae7e59 - build/sim: allow for arbitrary clocks generation using clockers <Jędrzej Boczar>
| * | 38054874 - build/sim: use a real timebase in the simulation <Jędrzej Boczar>
* | | e0f131a3 - cores/uart: add txempty/rxfull CSRs. <Florent Kermarrec>
* | | 2a3e39b1 - tools/litex_server: enable read_merger with CommUDP. <Florent Kermarrec>
* | | a5d0a340 - test: specify wishbone adr_width on AXI(Lite)<-->Wishbone tests and remove debug traces. <Florent Kermarrec>
* | | eb3374d0 - Merge pull request timvideos#617 from gsomlo/gls_rocket_dma <enjoy-digital>
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| * | | 561331ed - debug: make CI print offending values <Gabriel Somlo>
| * | | df3428be - liblitesdcard/sdcard: (temporarily) slow down SDCARD_CLK_FREQ to 25MHz <Gabriel Somlo>
| * | | 2d9dc8f9 - cores/cpu/rocket: expose slave port for DMA <Gabriel Somlo>
| * | | d8161e5a - integration/soc: make DMA slave region cover (at least) the lower 4GB <Gabriel Somlo>
| * | | 70eae5cb - interconnect/wishbone: increase WB address width to 31 <Gabriel Somlo>
| * | | b8c9da81 - soc/interconnect/axi: add Wishbone2AXI converter <Gabriel Somlo>
|/ / /
* | | 2ec4604c - cores/gpio: add support for Record on GPIOOut, GPIOIn and GPIOInOut. <Florent Kermarrec>
* | | 5e53e5d7 - Merge pull request timvideos#615 from pepijndevos/openfpgaloader <enjoy-digital>
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| * | | 79ca4d96 - remove debugging <Pepijn de Vos>
| * | | f6e20700 - add openFPGAloader programmer <Pepijn de Vos>
* | | | eab0726c - cpu/vexriscv/core: use variant name as human_name. <Florent Kermarrec>
* | | | e0a763e5 - cpu/vexriscv/system.h: provide empty flush_cpu_i/dcache functions for variants with no i/d cache. <Florent Kermarrec>
* | | | 3ff1bcaf - cpu/zynq7000: set csr map to 0x00000000. <Florent Kermarrec>
* | | | c0253e3f - Merge pull request timvideos#611 from antmicro/jboc/axi-lite <enjoy-digital>
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| | |/ /
| |/| |
| * | | e78d950a - soc/interconnect/axi: add AXILite -> AXI converter <Jędrzej Boczar>
* | | | cc844054 - tools/litex_server/read_merger: review/simplify a bit. <Florent Kermarrec>
* | | | 4f382ccf - Merge pull request timvideos#605 from cklarhorst/feature-uart-read-merger <enjoy-digital>
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| * | | | 2034c563 - Merge sequential reads for the UART litex_server backend <Christian Klarhorst>
* | | | | a942e358 - cpu/blackparrot: minor cleanups, add sim variant (since use different flist). <Florent Kermarrec>
| |_|_|/
|/| | |
* | | | 86e910df - Merge pull request timvideos#610 from Dolu1990/vexriscv_smp <enjoy-digital>
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| * | | | 023ab15e - soc/cores/cpu/vexriscv_smp enable dynamic litedram datawidth <Dolu1990>
| * | | | e5cd5d54 - Merge branch 'master' into vexriscv_smp <Dolu1990>
| |\ \ \ \
| |/ / / /
|/| | | |
* | | | | 1938ce36 - integration/soc/add_sdram: allow the CPU to add the direct memory buses when adding the sdram. <Florent Kermarrec>
* | | | | 6576416b - cores/cpu/rocket: add use_memory_bus parameter to easily disable direct memory bus for testing. <Florent Kermarrec>
| * | | | 789a70e7 - Merge branch 'master' into vexriscv_smp <Dolu1990>
| |\ \ \ \
| |/ / / /
|/| | | |
* | | | | 0696b409 - CHANGES: update. <Florent Kermarrec>
* | | | | fe38e12b - cpu/vexriscv_smp: move litedram import, remove os.path import. <Florent Kermarrec>
* | | | | 59b95fad - litex_setup: fix vexriscv-smp repository. <Florent Kermarrec>
* | | | | 9d052f38 - Merge pull request timvideos#607 from Dolu1990/vexriscv_smp <enjoy-digital>
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| | * | | | d284dfbe - soc/cores/cpu/vexriscv_smp config update <Dolu1990>
| |/ / / /
| * / / / aa57c7a2 - soc/cores/cpu/vexriscv_smp integration <Dolu1990>
|/ / / /
* | | | f87513ab - liblitesdcard/sdcard: increase SDCARD_CLK_FREQ to 50MHz. <Florent Kermarrec>
* | | | 9518ccf4 - integration/soc/etherbone: expose ethcore (useful to combine udp/etherbone). <Florent Kermarrec>
| |_|/
|/| |
* | | 9e07623b - integration/soc: fix dma_bus typo. <Florent Kermarrec>
|/ /
* / 1fdffdfd - targets: keep in sync with litex-boards. <Florent Kermarrec>
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* 8a0684b1 - Merge pull request timvideos#604 from antmicro/jboc/axi-lite <enjoy-digital>
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| * 879e6ffe - soc/interconnect/axi: add basic AXI Lite up-converter <Jędrzej Boczar>
| * 32160e61 - soc/interconnect/axi: separate AXI Lite converter channels <Jędrzej Boczar>
* | ed721198 - Merge pull request timvideos#603 from enjoy-digital/socdoc-extensions <Sean Cross>
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| * | 29b2baf9 - doc: socdoc: document new `sphinx_extra_config` parameter <Sean Cross>
| * | dd366467 - litex: add `sphinx_extra_config` to `generate_docs()` <Sean Cross>
* | | 3d16838d - Merge pull request timvideos#602 from enjoy-digital/socdoc-extensions <enjoy-digital>
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| * | 7fecfbf8 - doc: socdoc: document `sphinx_extensions` parameter <Sean Cross>
|/ /
* | 83370399 - CHANGES: update. <Florent Kermarrec>
* | 041c7527 - core/cpu: integrate Zynq as a classical CPU (Zynq7000), deprecate SoCZynq. <Florent Kermarrec>
|/
* 8bdf6941 - liblitesdcard/sdcard: use max divider of 256 (128 was not enough for the initial 400Khz clock frequency). <Florent Kermarrec>
* 8f92034d - CHANGES: update. <Florent Kermarrec>
* 99e88dfc - Merge pull request timvideos#600 from antmicro/jboc/axi-lite <enjoy-digital>
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| * a9d8b813 - test/axi: move all AXI Lite tests to separate file <Jędrzej Boczar>
| * 367eb122 - soc/integration: use AXILiteSRAM when using bus_standard="axi-lite" <Jędrzej Boczar>
| * 8ae501c3 - test/axi: add crossbar stress tests <Jędrzej Boczar>
| * 706bc25d - soc/integration: add bus standard parser arguments <Jędrzej Boczar>
| * 32d9e212 - soc/interconnect/axi: improve Timeout module and test it with shared interconnect <Jędrzej Boczar>
| * 2cab7fbf - test/axi: add shared AXI Lite interconnect tests <Jędrzej Boczar>
| * 3a08b21d - soc/interconnect/axi: implement AXI Lite decoder <Jędrzej Boczar>
| * 214cfdca - soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to <Jędrzej Boczar>
| * baf23c9c - test/test_axi: add AXI Lite interconnect arbiter tests <Jędrzej Boczar>
| * a8a583d6 - socinterconnect/axi: interconnect shared sketch <Jędrzej Boczar>
| * f47ccdae - soc/interconnect/axi: point-to-point interconnect and timeout module with tests <Jędrzej Boczar>
| * b4c1120e - soc/integration: choose interconnect based on bus standard <Jędrzej Boczar>
| * 69d8dd78 - soc/integration: add axi-lite standard to SoCBusHandler <Jędrzej Boczar>
* | d38048ba - soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). <Florent Kermarrec>
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* 2361abb1 - Merge pull request timvideos#599 from antmicro/gen-mmcm-pr <enjoy-digital>
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| * 66c5f371 - litex-gen: add mmcm core <Piotr Binkowski>
* 6b72f52c - boards: keep in sync with litex-boards. <Florent Kermarrec>
* 1f27b740 - soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. <Florent Kermarrec>
* 408d1a9f - cpu/vexriscv/system.h: update flush_cpu_dcache. <Florent Kermarrec>
* 47ce15b4 - interconnect/wishbone: add minimal UpConverter. <Florent Kermarrec>
* litex-boards changed from 2ce24df to 2020.08-9-g63b65e2
* 63b65e2 - crosslink_nx_evn: update copyrights. <Florent Kermarrec>
* 153326f - targets/icebreaker: update flash. <Florent Kermarrec>
* 795e34a - add initial Crosslink-NX support. <Piense>
* 84c19a6 - targets/de0nano: set sys2x_ps phase to 180° for sdram_rate=1:2. <Florent Kermarrec>
* 70594a5 - ulx3s: simplify sdram constraints and increase phase to 180 for sdram_rate=1:2. <Florent Kermarrec>
* 1781be1 - general: add SPDX License identifier to header and specify files are part of LiteX-Boards. <Florent Kermarrec>
* 83d8b8d - platforms/acorn_cle_215: integrated sdcard ios as extension. <Florent Kermarrec>
* d365836 - Merge pull request timvideos#100 from connorwk/master <enjoy-digital>
|\
| * f328909 - Moved platform call inside of BaseSoC init for compatibility with linux-on-litex-vexriscv support. Added optional spi-sdcard support over P2 header. <connorwk>
|/
* 45bb329 - targets/colorlight_5a_75x: enable HalfRate SDRAM PHY. <Florent Kermarrec>
* b6a1ad5 - targets/orangecrab: add simple CRG when built without DDR3. <Florent Kermarrec>
* 869cead - targets: use platform.request_all on LedChaser. <Florent Kermarrec>
* 8583c44 - Merge pull request timvideos#98 from antmicro/arty_pmod_configuration <enjoy-digital>
|\
| * d2cd6d4 - arty: Change USB-uart and I2S Pmod configuration <Pawel Sagan>
|/
* ee28d7b - targets/ulx3s/add_oled: simplify. <Florent Kermarrec>
* 623faa9 - Merge pull request timvideos#96 from pepijndevos/oled <enjoy-digital>
|\
| * eba7037 - add optional OLED peripheral to ULX3S target <Pepijn de Vos>
|/
* 929e55d - platforms/trellisboard: add SDCard PMOD pins. <Florent Kermarrec>
* 5fd3e8d - ecpix5: add SDCard. <Florent Kermarrec>
* f058181 - README: fix typo. <Florent Kermarrec>
* 94ccf1d - targets/trellisboard: simplify clocking when no DDR3, remove firmware_ram (was here for debug). <Florent Kermarrec>
* ecdc1ef - README: add missings . <Florent Kermarrec>
* 361afa7 - README: add links to LiteX's wiki. <Florent Kermarrec>
* 02c0c0a - README: add board picture and fix a few typos. <Florent Kermarrec>
* eb8a484 - targets/de10nano: fix typo. <Florent Kermarrec>
* 2cef54a - targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). <Florent Kermarrec>
* bfbee48 - Readme/boards: fill most of the missing infos. <Florent Kermarrec>
* bb65692 - add LICENSE. <Florent Kermarrec>
* e9706d4 - README: add initial contents and list of supported boards. <Florent Kermarrec>
* 760b8ff - arty: improve xy_pmod_io genericity (allow selecting the PMOD) and enable SDCard. <Florent Kermarrec>
* 04fc98f - de0nano/ulx3s: add sdram HalfRate support (untested). <Florent Kermarrec>
* d0ca1be - targets/de10nano/minispartan6: simplify HalfRate support, rename argument to sdram_rate. <Florent Kermarrec>
* 9730c6f - platforms/de10nano: use additional sdram constraints required for HalfRate. <Florent Kermarrec>
* 7399d13 - paltforms/de10nano/sdram: enable fast input/output on dq. <Florent Kermarrec>
* b4b1ab8 - paltforms/de10nano: simplify IO constraints (for consistency with others platforms). <Florent Kermarrec>
* 89c5bf4 - Merge pull request timvideos#92 from rob-ng15/master <enjoy-digital>
|\
| * 7cda143 - Allow use of HalfRateGENSDRPHY <rob-ng15>
| * cf98393 - Add Misc <rob-ng15>
* | 1e1589a - zybo_z7: demonstrate use of PS7 (with --cpu-type=zynq7000). <Florent Kermarrec>
* | 8a3b453 - add Zybo Z7 minimal platform/targets: no PS7 support and USB-UART PMOD on JB. <Florent Kermarrec>
|/
* e723bef - platforms/arty: add usb_uart_pmod_io (USB-UART PMOD on JA) to ease debug with a second UART (for UARTbone/LiteScope). <Florent Kermarrec>
* 19d0b95 - platforms/targets: keep in sync with litex. <Florent Kermarrec>
* 0ee4b21 - trellisboard/ulx3s: fix sdcard slewrate. <Florent Kermarrec>
* 7efa1c3 - platforms/arty: add missing pullups on sdcard. <Florent Kermarrec>
* litex-renode changed from f179258 to 3d01f40
* 3d01f40 - Merge pull request timvideos#29 from antmicro/i2c_generation <Mateusz Hołenko>
* ed34c42 - generate-renode-scripts: Add I2C support <Mateusz Holenko>
* a431211 - generate-zephyr-dts: Add I2C support <Mateusz Holenko>
* 9f4f0fb - [FIX] Fix config generation <Mateusz Holenko>
* nmigen changed from 8f5a253 to 1ad6e32
* 1ad6e32 - Clifford -> Claire <Sebastien Bourdeauducq>
* 40f7f12 - Add option to specify solver in nmigen.test.utils <Donald Sebastian Leung>
Full submodule status
--
2942d0652a89646c5225bee15dd55cc3b0871766 VexRiscv (1.0.1-417-g2942d06)
3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (heads/master)
3a06aa84b62ad24467fb0d2c6ceddf565e9ea447 flash_proxies (heads/master)
5c69da5d6db245dedab479509c0eaa8c1c80027c litedram (2020.08-3-g5c69da5)
54acf9fd76c226d7760294ffde86418e52e0951b liteeth (2020.04-26-g54acf9f)
efd200fa9e625144131a310fc09fd1fecf1682e6 liteiclink (2020.08-1-gefd200f)
0718fd135fc30e0a3598eaf66ce2fcb54b62193c litepcie (2020.08-1-g0718fd1)
ba006a78c12e25354dafb021510c043dbe070614 litesata (2020.08-1-gba006a7)
02b543e5ba24c025212515f6e32f542629d823e8 litescope (2020.08-2-g02b543e)
7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (heads/master)
41f30143075ece3fff5c33a332ed067d1837cbb3 litevideo (2020.04)
3897acb9e4b91ad58abbcea8e3cff6e44223bd02 litex (2020.04-639-g3897acb9)
63b65e278c279a9cf8c4da31db8f7e845edba394 litex-boards (2020.08-9-g63b65e2)
3d01f408539b4641f9d2b42ebd8237436e49d16b litex-renode (remotes/origin/HEAD)
7bc4eb1387b39159a74c1dbd1b820728e0bfbbaa migen (0.6.dev-354-g7bc4eb1)
1ad6e3207f02e913407867dddddb8f50fad0ced4 nmigen (v0.1-71-g1ad6e32)
48333804e40c7c9c1c8d5b2e70ba75f4b646d8f0 pythondata-cpu-lm32 (2020.08)
4731142284cf87e89b21fb35ceff1139f2f89227 pythondata-cpu-minerva (2020.08)
af561171f5fc8c684537897f12ef0f429e38624b pythondata-cpu-mor1kx (2020.08)
88974894c800ee2e827db47865e0611a07ff40d7 pythondata-cpu-picorv32 (2020.08)
654057b2f5cec0f9fc99487dff67861f76fcbe7e pythondata-cpu-vexriscv (2020.08)
7cfcaed2e726027fd622650b58dd77e47c495ee0 pythondata-software-compiler_rt (2020.08)
da4c8c72eeb22894369b3936abb73f828f222b8e valentyusb (v0.3.3-195-gda4c8c7)
|
Superseded by #633. |
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Bumps third_party/liteeth from
54acf9fto7448170.Commits
7448170liteth/phy/rmii: add support for ref_clk as input.dea3590phy/rmii: add refclk_cd parameter (to select reference eth clock domain) and ...617400ftest/test_etherbone: disable for now (hanging).e270956test/test_model: fix test_etherbone.d901027bench/test_etherbone/speed_test: use burst_size of 255.d3788cdfrontend/etherbone: use new LiteX's PacketFIFO in LiteEthEtherboneRecordSender.d3ae361bench/sim: fix sim ethernet tap ip address.3afd62ebench: add sim (with similar features than hardware targets).faf7896bench/test_etherbone: allow direct CommUDP use with --udp.5abf44dbench/targets: set buffer_depth to 255 (max).Dependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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