Must-have verilog systemverilog modules
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Updated
Jul 6, 2024 - Verilog
Must-have verilog systemverilog modules
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
5 Day TCL begginer to advanced training workshop by VSD
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
Scan insertion and design of a LBIST wrapper for a RISC-V core for stuck-at fault model
Complete design of a Mini Stereo Digital Audio Processor
✅ Formal verification of a 16-bit SIMD processor
Contains some TCL scriping language excercises + 2 university contests on HIgh Level Synthesis (winner contest) and Logic Level Synthesis
ALEF_Vivado (Automated Library Evaluation Framework) is a tool coded up in Python that automates the synthesis and implementation flow of Xilinx Vivado Tool by running Tcl Scripts for the input Verilog/SystemVerilog modules and finally generating a CSV file containing several components of the generated power, timing, and utilization reports.
5-Day TCL begginer to advanced workshop by VSD
TCL Script automating the frontend of ASIC design
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
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