Skip to content
chipyard-ci-full-flow

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1415

Sign in to view logs

Support Chisel6 for RTL-sim/VLSI/FPGA flows

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1415

Triggered via pull request May 13, 2024 19:48
@jerryz123jerryz123
synchronize #1854
chisel6-attempt2
Status Success
Total duration 21m 52s
Artifacts –

chipyard-full-flow.yml

on: pull_request
cancel-prior-workflows
cancel-prior-workflows
filter-jobs-on-changes
filter-jobs-on-changes
full-flow
21m 21s
full-flow
cleanup
6s
cleanup
Fit to window
Zoom out
Zoom in

Annotations

1 warning
full-flow
Node.js 16 actions are deprecated. Please update the following actions to use Node.js 20: actions/checkout@v3. For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.