Merge pull request #1537 from ucb-bar/vlsi-fixes

VLSI Fixes
ucb-bar · Jul 1, 2023 · ea26b02 · ea26b02
2 parents 2ba1198 + 2220599
commit ea26b02
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Showing 8 changed files with 10 additions and 10 deletions.
diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml
@@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"}
+  {name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"}
 ]
 
 # Generate Make include to aid in flow

diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml
@@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"}
+  {name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"}
 ]
 
 # Specify pin properties

diff --git a/vlsi/example-designs/sky130-commercial.yml b/vlsi/example-designs/sky130-commercial.yml
@@ -2,7 +2,7 @@
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "30ns", uncertainty: "2ns"}
+  {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
 ]
 
 # Placement Constraints
@@ -16,4 +16,4 @@ vlsi.inputs.clocks: [
 #     - path: "ChipTop"
 #       ...
 #       margins:
-#         right: 0  # or left: 0
+#         right: 0  # or left: 0
diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -1,7 +1,7 @@
 # Override configurations in ../example-sky130.yml and example-designs
 
 # Specify clock signals
-# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
 vlsi.inputs.clocks: [
   {name: "clock", period: "30ns", uncertainty: "3ns"}
 ]

diff --git a/vlsi/example-designs/sky130-openroad.yml b/vlsi/example-designs/sky130-openroad.yml
@@ -3,7 +3,7 @@
 # Specify clock signals
 # Relax the clock period for OpenROAD to meet timing
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "50ns", uncertainty: "2ns"}
+  {name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
 ]
 
 # Flow parameters that yield a routable design with reasonable timing

diff --git a/vlsi/example-designs/sky130-rocket.yml b/vlsi/example-designs/sky130-rocket.yml
@@ -1,7 +1,7 @@
 # Override configurations in ../example-sky130.yml and example-designs
 
 # Specify clock signals
-# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
 vlsi.inputs.clocks: [
   {name: "clock", period: "5ns", uncertainty: "1ns"}
 ]

diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml
@@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "20ns", uncertainty: "1ns"}
+  {name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
 ]
 
 # Generate Make include to aid in flow

diff --git a/vlsi/sim.mk b/vlsi/sim.mk
@@ -21,7 +21,7 @@ $(SIM_CONF): $(sim_common_files) check-binary
 	done
 	echo "  options_meta: 'append'" >> $@
 	echo "  defines:" >> $@
-	for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
+	for x in $(subst +define+,,$(SIM_PREPROC_DEFINES)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  defines_meta: 'append'" >> $@
@@ -75,7 +75,7 @@ $(SIM_TIMING_CONF): $(sim_common_files)
 	echo "sim.inputs:" > $@
 	echo "  defines: ['NTC']" >> $@
 	echo "  defines_meta: 'append'" >> $@
-	echo "  timing_annotated: 'true'" >> $@
+	echo "  timing_annotated: true" >> $@
 
 # Update hammer top-level sim targets to include our generated sim configs
 redo-sim-rtl: $(SIM_CONF)