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Update google_riscv-dv to chipsalliance/riscv-dv@ea8dd25
Update code from upstream repository https://github.com/google/riscv- dv to revision ea8dd25140178eed13c3e0f3d3a97a0c07ab44a0 * Upgrade bitmanip v.0.92 to v.0.93, enable simultaneous use with v.1.00 (Pirmin Vogel) * Added v1.0.0 bitmanip support (Henrik Fegran) * Remove the pyucis-viewer from requirements.txt (aneels3) * Update README.md for PyFlow & add pyucis-viewer in requiremen.txt (aneels3) * Fix typo with fs3_sign (aneels3) * Add hint_cg and illegal_compressed_instr_cg covergroups (aneels3) * override deepcopy method (aneels3) * Fix issue with illegal_instr_testi and randselect (aneels3) * Fixed b_extension_c() issue (shrujal20) * Fixed get_rand_spf_dpf_value() issue (shrujal20) * Add support for RV32C coverage (aneels3) * Add README.md for PyFlow (aneels3) * Add gen_timeout for PyFlow (aneels3) * Issue chipsalliance/riscv-dv#778 fix, change mie behavior in setup_mmode_reg (Henrik Fegran) * Fixed wrong length of I, S, B-type immediates causing wrong sign extension for certain instructions (Henrik Fegran) * Update riscv_compressed_instr.sv (AryamanAg) * Update var binary of function convert2bin (AryamanAg) * Improve status reporting (Philipp Wagner) * update ml/testlist.yaml to get better coverage (Udi Jonnalagadda) * add m extension covgroup (ishita71) * Update pygen_src files (aneels3) Signed-off-by: Pirmin Vogel <[email protected]>
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## Overview | ||
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RISCV-DV-PyFlow is a purely Python based open-source instruction generator for RISC-V processor | ||
verification. It uses [PyVSC](https://github.com/fvutils/pyvsc) as the main library for | ||
randomization and coverage collection. It currently supports the following features: | ||
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- Supported instruction set: RV32IMAFDC | ||
- Supported privileged modes: For now only machine mode is supported. | ||
- Illegal instruction and HINT instruction generation | ||
- Random forward/backward branch instructions | ||
- Supports mixing directed instructions with random instruction stream | ||
- Support for direct & vectored interrupt table. | ||
- Multi-hart support | ||
- Functional coverage framework (reports GUI as well as text, currently | ||
supports RV32IMFDC extensions) | ||
- Supported ISS : Spike, OVPsim | ||
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## Supported tests | ||
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- riscv_arithmetic_basic_test | ||
- riscv_amo_test | ||
- riscv_floating_point_arithmetic_test | ||
- riscv_floating_point_rand_test | ||
- riscv_floating_point_mmu_stress_test | ||
- riscv_b_ext_test | ||
- riscv_rand_instr_test | ||
- riscv_jump_stress_test | ||
- riscv_rand_jump_test | ||
- riscv_mmu_stress_test | ||
- riscv_illegal_instr_test | ||
- riscv_unaligned_load_store_test | ||
- riscv_single_hart_test | ||
- riscv_non_compressed_instr_test | ||
- riscv_loop_test | ||
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## Getting Started | ||
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### Prerequisites | ||
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To be able to run the generator, you need to have RISCV-GCC compiler toolchain and ISS | ||
(Instruction Set Simulator) installed (Spike is preferred). | ||
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### Install RISCV-DV-PyFlow | ||
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Getting the source | ||
```bash | ||
git clone https://github.com/google/riscv-dv.git | ||
``` | ||
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```bash | ||
pip3 install -r requirements.txt # install dependencies (only once) | ||
python3 run.py --help | ||
``` | ||
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## Running the Generator | ||
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Command to run a single test: | ||
```bash | ||
python3 run.py --test=riscv_arithmetic_basic_test --simulator=pyflow | ||
``` | ||
--simulator=pyflow will invoke the Python generator. | ||
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Run a single test 10 times | ||
```bash | ||
python3 run.py --test=riscv_arithmetic_basic_test --iterations=10 --simulator=pyflow | ||
``` | ||
Run the generator only, do not compile and simluation with ISS | ||
```bash | ||
python3 run.py --test=riscv_arithmetic_basic_test --simulator=pyflow --steps gen | ||
``` | ||
## Coverage Model | ||
The coverage model of PyFlow is developed using PyVSC library. | ||
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Command to generate the coverage report. | ||
#### Process spike simulation log and collect functional coverage | ||
```bash | ||
python3 cov.py --dir out/spike_sim/ --simulator=pyflow --enable_visualization | ||
``` | ||
--enable_visualization helps enabling coverage report visualization for pyflow. | ||
#### Get the command reference | ||
```bash | ||
cov --help | ||
``` | ||
#### Run the coverage flow with predefined targets | ||
```bash | ||
python3 cov.py --dir out/spike_sim/ --simulator=pyflow --enable_visualization --target rv32imc | ||
``` | ||
The coverage reports can be viewed using two ways: | ||
1) Text format: By opening the CoverageReport.txt file. | ||
2) GUI format: By opening the cov_db.xml using pyucis-viewer. | ||
The GUI format could be enabled using "--enable_visualization" command option. | ||
```bash | ||
pyucis-viewer cov_db.xml | ||
``` | ||
## Note | ||
Currently, time to generate a single program with larger than 10k instructions is around | ||
12 minutes. We are working on improving the overall performance. |
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@@ -223,6 +223,6 @@ def conver2bin(self, prefix=""): | |
def get_c_opcode(self): | ||
pass | ||
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# TOD0 | ||
# TODO | ||
def get_func3(self): | ||
pass |
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